Datasheet > IN74ACT112

IN74ACT112

更新时间： 2024-11-06 11:20:11

品牌	Logo	应用领域
IKSEMICON		触发器栅
页数	文件大小	规格书
6页	228K
描述
Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

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中文翻译

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数据手册

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IN74ACT112 数据手册

TECHNICAL DATA

IN74ACT112

Dual J-K Flip-Flop

with Set and Reset

High-Speed Silicon-Gate CMOS

The IN74ACT112 is identical in pinout to the LS/ALS112,

HC/HCT112. The IN74ACT112 may be used as a level converter for

interfacing TTL or NMOS outputs to High Speed CMOS inputs.

Each flip-flop is negative-edge clocked and has active-low

asynchronous Set and Reset inputs.

•

TTL/NMOS Compatible Input Levels

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 4.5 to 5.5 V

Low Input Current: 1.0 μA; 0.1 μA @ 25°C

Outputs Source/Sink 24 mA

ORDERING INFORMATION

IN74ACT112N Plastic

IN74ACT112D SOIC

T_A= -40° to 85° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Clock

Outputs

Set

Reset

L^*

No Change

Toggle

No Change

* Both outputs will remain low as long as Set and Reset are

low, but the output states are unpredictable if Set and Reset

go high simultaneously

PIN 16=V_CC

PIN 8 = GND

X = Don’t Care

Rev. 00

12 3 4 5 6

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与IN74ACT112相关器件

型号	品牌	获取价格	描述	数据表
IN74ACT112D	IKSEMICON	获取价格	Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS
IN74ACT112D	INTEGRAL	获取价格	DUAL J-K FLIP-FLOP WITH SET AND RESET
IN74ACT112N	INTEGRAL	获取价格	DUAL J-K FLIP-FLOP WITH SET AND RESET
IN74ACT112N	IKSEMICON	获取价格	Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS
IN74ACT11D	INTEGRAL	获取价格	TRIPLE 3-INPUT AND GATE
IN74ACT11N	INTEGRAL	获取价格	TRIPLE 3-INPUT AND GATE
IN74ACT125	INTEGRAL	获取价格	Quad 3-State Noninverting Buffers
IN74ACT125	IKSEMICON	获取价格	Quad 3-State Noninverting Buffers High-Speed Silicon-Gate CMOS
IN74ACT125D	IKSEMICON	获取价格	Quad 3-State Noninverting Buffers High-Speed Silicon-Gate CMOS
IN74ACT125D	INTEGRAL	获取价格	Quad 3-State Noninverting Buffers