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IN74ACT112N PDF预览

IN74ACT112N

更新时间: 2024-11-05 22:48:07
品牌 Logo 应用领域
INTEGRAL 触发器
页数 文件大小 规格书
5页 204K
描述
DUAL J-K FLIP-FLOP WITH SET AND RESET

IN74ACT112N 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.75
Base Number Matches:1

IN74ACT112N 数据手册

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IN74ACT112  
DUAL J-K FLIP-FLOP  
WITH SET AND RESET  
High-Speed Silicon-Gate CMOS  
The IN74ACT112 is identical in pinout to the LS/ALS112,  
HC/HCT112. The IN74ACT112 may be used as a level converter  
for interfacing TTL or NMOS outputs to High Speed CMOS  
inputs.  
Each flip-flop is negative-edge clocked and has active-low  
asynchronous Set and Reset inputs.  
TTL/NMOS Compatible Input Levels  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 4.5 to 5.5 V  
Low Input Current: 1.0 µA; 0.1 µA @ 25°C  
Outputs Source/Sink 24 mA  
ORDERING INFORMATION  
IN74ACT112N Plastic  
IN74ACT112D SOIC  
TA = -40° to 85° C for all  
packages  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
FUNCTION TABLE  
Inputs  
Outputs  
Set  
Reset  
Clock  
J
K
Q
Q
L
H
L
H
H
H
H
H
H
H
H
X
X
X
X
X
X
L
X
X
X
L
H
L
H
L*  
L
L
L
L*  
H
H
H
H
H
H
H
No Change  
L
H
L
L
H
H
L
H
H
X
X
X
H
X
X
X
Toggle  
L
H
No Change  
No Change  
No Change  
PIN 16=VCC  
PIN 8 = GND  
* Both outputs will remain low as long as Set and  
Reset are low, but the output states are  
unpredictable if Set and Reset go high  
simultaneously  
X = Don’t Care  
1

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