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IDT74FCT162652TPA8 PDF预览

IDT74FCT162652TPA8

更新时间: 2024-10-29 20:59:55
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路
页数 文件大小 规格书
9页 110K
描述
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TSSOP-56

IDT74FCT162652TPA8 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:56
Reach Compliance Code:unknown风险等级:5.35
系列:FCTJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:14 mm
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER位数:8
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL宽度:6.1 mm
Base Number Matches:1

IDT74FCT162652TPA8 数据手册

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FAST CMOS 16-BIT  
BUS TRANSCEIVER/  
REGISTER  
IDT54/74FCT162652T/AT/CT  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
High-speed, low-power CMOS replacement for ABT functions  
Typical tSK(o) (Output Skew) < 250ps  
Low input and output leakage 1µA (max.)  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
VCC = 5V ±10%  
The FCT162652T16-bitregisteredtransceivers are builtusingadvanced  
dual metal CMOS technology. These high-speed, low-power devices are  
organized as two independent 8-bit bus transceivers with 3-state D-type  
registers.Forexample,thexOEABandxOEBAsignalscontrolthetransceiver  
functions.  
The xSAB and xSBA control pins are provided to select either real time or  
storeddatatransfer. Thecircuitryusedforselectcontrolwilleliminatethetypical  
decodingglitchthatoccursinamultiplexerduringthetransitionbetweenstored  
andrealtimedata.Alowinputlevelselectsreal-timedataandahighlevelselects  
storeddata.  
• Balanced Output Drivers:  
– ±24mA(industrial)  
– ±16mA(military)  
• Reduced system switching noise  
Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,  
TA = 25°C  
Available in the following packages:  
Industrial: SSOP, TSSOP  
DataontheAorBdatabus,orboth,canbestoredintheinternalD-flip-flops  
bylow-to-hightransitionsattheappropriateclockpins(xCLKABorxCLKBA),  
regardless ofthe selectorenable controlpins. Flow-throughorganizationof  
signalpinssimplifieslayout.Allinputsaredesignedwithhysteresisforimproved  
noisemargin.  
Military: CERPACK  
TheFCT162652Thasbalancedoutputdrivewithcurrentlimitingresistors.  
Thisofferslowgroundbounce,minimalundershoot,andcontrolledoutputfall  
times–reducing the need for external series terminating resistors. The  
FCT162652Tisaplug-inreplacementfortheFCT16652TandABT16652for  
on-boardbusinterfaceapplications.  
FUNCTIONALBLOCKDIAGRAM  
2OEAB  
1OEAB  
2OEBA  
1OEBA  
2CLKBA  
1CLKBA  
1SBA  
2SBA  
2CLKAB  
1CLKAB  
2SAB  
B REG  
D
1SAB  
B REG  
D
C
C
1B1  
A REG  
2B1  
A REG  
2A1  
1A1  
D
D
C
C
TO SEVEN OTHER CHANNELS  
TO SEVEN OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
MILITARY AND INDUSTRIAL TEMPERATURE RANGES  
JUNE 2002  
1
© 2002 Integrated Device Technology, Inc.  
DSC-5451/4  

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