IDT54/74FCT162701T/AT
FAST CMOS 18-BIT
R/W BUFFER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
The FCT162701T/AT is an 18-bit Read/Write buffer with
a four deep FIFO and a read-back latch. It can be used as
a read/write buffer between a CPU and memory or to
interface a high-speed bus and a slow peripheral. The A-
to-B (write) path has a four deep FIFO for pipelined opera-
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤1µA (max.)
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packagesinclude25milpitchSSOP, 19.6milpitchTSSOP, tions. The FIFO can be reset and a FIFO full condition is
15.7 mil pitch TVSOP and 25 mil pitch Cerpack
• Extended commercial range of -40°C to +85°C
indicated by the full flag (FF). The B-to-A (read) path has a
latch. A HIGH on LE, allows data to flow transparently from
B-to-A. A LOW on LE allows the data to be latched on the
falling edge of LE.
• Balanced Output Drivers:
±24mA (commercial),
±16mA (military)
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V, TA = 25°C
The FCT162701T/AT has a balanced output drive with
series termination. This provides low ground bounce,
minimal undershoot and controlled output edge rates.
• Ideal for new generation x86 write-back cache solutions
• Suitable for modular x86 architectures
• Four deep write FIFO
• Latch in read path
• Synchronous FIFO reset
FUNCTIONAL BLOCK DIAGRAM
A1-18
18
OEBA
RESET
CLK
LE
FIFO
(4 deep)
LATCH
WCE
RCE
FF
OEAB
18
2915 drw 01
B
1-18
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1996
1996 Integrated Device Technology, Inc.
5.15
DSC-2915/3
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