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IDT74FCT162701ATPV8 PDF预览

IDT74FCT162701ATPV8

更新时间: 2024-10-29 19:41:31
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片光电二极管
页数 文件大小 规格书
8页 60K
描述
FIFO, 4X18, 5.2ns, Synchronous, CMOS, PDSO56, SSOP-56

IDT74FCT162701ATPV8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP-56
针数:56Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:5.2 ns
周期时间:6 nsJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:18.415 mm
内存密度:72 bit内存宽度:18
湿度敏感等级:1功能数量:1
端子数量:56字数:4 words
字数代码:4工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4X18输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP56,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
座面最大高度:2.794 mm子类别:Other Memory ICs
最大压摆率:0.005 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:7.5 mmBase Number Matches:1

IDT74FCT162701ATPV8 数据手册

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FAST CMOS 18-BIT  
IDT74FCT162701T/AT  
READ/WRITE BUFFER  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
• Typical tSK(o) (Output Skew) < 250ps  
• Low input and output leakage 1µA (max.)  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• Balanced Output Drivers (±24mA)  
• Reduced system switching noise  
• Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,  
TA = 25°C  
TheFCT162701Tisan18-bitRead/WritebufferwithafourdeepFIFOand  
a read-back latch. It can be used as a read/write buffer between a CPU and  
memory or to interface a high-speed bus and a slow peripheral. The A-to-B  
(write) path has a four deep FIFO for pipelined operations. The FIFO can be  
resetandaFIFOfullconditionisindicatedbythefullflag(FF). TheB-to-A(read)  
pathhasalatch. AhighonLE,allowsdatatoflowtransparentlyfromB-to-A.  
A low on LE allows the data to be latched on the falling edge of LE.  
The FCT162701T has a balanced output drive with series termination.  
Thisprovideslowgroundbounce,minimalundershootandcontrolledoutput  
edgerates.  
• Ideal for new generation x86 write-back cache solutions  
• Suitable for modular x86 architectures  
• Four deep write FIFO  
• Latch in read path  
• Synchronous FIFO reset  
• Available in SSOP package  
FUNCTIONALBLOCKDIAGRAM  
A1-18  
18  
OEBA  
RESET  
CLK  
LE  
FIFO  
(4 deep)  
LATCH  
WCE  
RCE  
FF  
OEAB  
18  
B1-18  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JANUARY 2004  
1
© 2004 Integrated Device Technology, Inc.  
DSC-2915/2  

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