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IDT74FCT162701TPA8 PDF预览

IDT74FCT162701TPA8

更新时间: 2024-10-29 20:55:43
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片光电二极管
页数 文件大小 规格书
8页 63K
描述
FIFO, 4X18, 6ns, Synchronous, CMOS, PDSO56, TSSOP-56

IDT74FCT162701TPA8 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:56
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.84
最长访问时间:6 ns周期时间:6 ns
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
长度:14 mm内存密度:72 bit
内存宽度:18功能数量:1
端子数量:56字数:4 words
字数代码:4工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4X18输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:6.1 mmBase Number Matches:1

IDT74FCT162701TPA8 数据手册

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FAST CMOS 18-BIT  
IDT74FCT162701T/AT  
READ/WRITE BUFFER  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
• Typical tSK(o) (Output Skew) < 250ps  
• Low input and output leakage 1µA (max.)  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• Balanced Output Drivers (±24mA)  
• Reduced system switching noise  
• Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,  
TA = 25°C  
TheFCT162701Tisan18-bitRead/WritebufferwithafourdeepFIFOand  
a read-back latch. It can be used as a read/write buffer between a CPU and  
memory or to interface a high-speed bus and a slow peripheral. The A-to-B  
(write) path has a four deep FIFO for pipelined operations. The FIFO can be  
resetandaFIFOfullconditionisindicatedbythefullflag(FF). TheB-to-A(read)  
pathhasalatch. AhighonLE,allowsdatatoflowtransparentlyfromB-to-A.  
A low on LE allows the data to be latched on the falling edge of LE.  
The FCT162701T has a balanced output drive with series termination.  
Thisprovideslowgroundbounce,minimalundershootandcontrolledoutput  
edgerates.  
• Ideal for new generation x86 write-back cache solutions  
• Suitable for modular x86 architectures  
• Four deep write FIFO  
• Latch in read path  
• Synchronous FIFO reset  
• Available in SSOP and TSSOP packages  
FUNCTIONALBLOCKDIAGRAM  
A1-18  
18  
OEBA  
RESET  
CLK  
LE  
FIFO  
(4 deep)  
LATCH  
WCE  
RCE  
FF  
OEAB  
18  
B1-18  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JANUARY 2002  
1
© 2002 Integrated Device Technology, Inc.  
DSC-2915/1  

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