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IDT74FCT162511ATEG PDF预览

IDT74FCT162511ATEG

更新时间: 2024-10-28 19:11:03
品牌 Logo 应用领域
艾迪悌 - IDT 输出元件逻辑集成电路
页数 文件大小 规格书
10页 180K
描述
Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56

IDT74FCT162511ATEG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DFP
包装说明:0.635 MM PITCH, CERPACK-56针数:56
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.83其他特性:INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B
系列:FCTJESD-30 代码:R-GDFP-F56
JESD-609代码:e3长度:18.415 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
位数:16功能数量:1
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):260传播延迟(tpd):5.6 ns
认证状态:Not Qualified座面最大高度:2.413 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:FLAT
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:9.652 mm
Base Number Matches:1

IDT74FCT162511ATEG 数据手册

 浏览型号IDT74FCT162511ATEG的Datasheet PDF文件第2页浏览型号IDT74FCT162511ATEG的Datasheet PDF文件第3页浏览型号IDT74FCT162511ATEG的Datasheet PDF文件第4页浏览型号IDT74FCT162511ATEG的Datasheet PDF文件第5页浏览型号IDT74FCT162511ATEG的Datasheet PDF文件第6页浏览型号IDT74FCT162511ATEG的Datasheet PDF文件第7页 
FAST CMOS 16-BIT  
IDT54/74FCT162511AT/CT  
REGISTERED/LATCHED  
TRANSCEIVER WITH PARITY  
DESCRIPTION:  
FEATURES:  
0.5 MICRON CMOS Technology  
TheFCT162511AT/CT16-bitregistered/latchedtransceiverwithparity  
isbuiltusingadvanceddualmetalCMOStechnology. Thishigh-speed,low-  
powertransceivercombines D-type latches andD-type flip-flops toallow  
dataflowintransparent,latched,orclockedmodes. Thedevicehasaparity  
generator/checkerinthe A-to-Bdirectionanda paritycheckerinthe B-to-  
Adirection. Errorcheckingisdoneatthebytelevelwithseparateparitybits  
foreachbyte. Separateerrorflagsexitsforeachdirectionwithasingleerror  
flagindicatinganerrorforeitherbyte inthe A-to-Bdirectionanda second  
errorflagindicatinganerrorforeitherbyteintheB-to-Adirection. Theparity  
errorflagsareopendrainoutputswhichcanbetiedtogetherand/ortiedwith  
flags fromotherdevices toforma single errorflagorinterrupt. The parity  
error flags are enabled by the OExx control pins allowing the designer to  
disable the errorflagduringcombinationaltransitions.  
Typical tsk(o) (Output Skew) < 250ps, clocked mode  
Low input and output leakage 1µA (max)  
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP  
and 25 mil pitch CERPACK packages  
Extended commercial range of –40°C to +85°C  
VCC = 5V ±10%  
Balanced Output Drivers:  
±24mA (commercial)  
±16mA (military)  
Series current limiting resistors  
Generate/Check, Check/Check modes  
Open drain parity error allows wire-OR  
The controlpins LEAB,CLKAB,andOEABcontroloperationinthe A-  
to-BdirectionwhileLEBA,CLKBA,andOEBAcontroltheB-to-Adirection.  
GEN/CHKisonlyfortheselectionofA-to-Boperation. TheB-to-Adirection  
is always incheckingmode. The ODD/EVEN selectis commonbetween  
the two directions. Except for the ODD/EVEN control, independent  
operation can be achieved between the two directions by using the  
correspondingcontrollines.  
FUNCTIONALBLOCKDIAGRAM  
LEAB  
CLKAB  
OEAB  
Data  
Parity, data  
B0-15  
16  
18  
PB1,2  
Parity  
Latch/  
Register  
GEN/CHK  
Byte  
2
Parity  
PERB  
Generator/  
Checker  
A0-15  
PA1,2  
(Open Drain)  
ODD/EVEN  
LEBA  
CLKBA  
Parity, Data  
18  
Parity, data  
18  
Latch/  
Register  
OEBA  
Byte  
Parity  
Checking  
PERA  
(Open Drain)  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-2916/5  

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