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IDT74FCT162511ATPVG PDF预览

IDT74FCT162511ATPVG

更新时间: 2024-10-28 19:44:19
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
10页 100K
描述
Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, PDSO56, GREEN, SSOP-56

IDT74FCT162511ATPVG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:GREEN, SSOP-56针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.43
其他特性:INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B系列:FCT
JESD-30 代码:R-PDSO-G56JESD-609代码:e3
长度:18.415 mm负载电容(CL):50 pF
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER湿度敏感等级:1
位数:16功能数量:1
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):5.6 ns
认证状态:Not Qualified座面最大高度:2.794 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

IDT74FCT162511ATPVG 数据手册

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FAST CMOS 16-BIT  
IDT54/74FCT162511AT/CT  
REGISTERED/LATCHED  
TRANSCEIVER WITH PARITY  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
The FCT162511T 16-bit registered/latched transceiver with parity is built  
usingadvanceddualmetalCMOStechnology. This high-speed, low-power  
transceivercombinesD-typelatchesandD-typeflip-flopstoallowdataflowin  
transparent, latched, or clocked modes. The device has a parity generator/  
checkerintheA-to-BdirectionandaparitycheckerintheB-to-Adirection. Error  
checkingisdoneatthebytelevelwithseparateparitybitsforeachbyte. Separate  
errorflagsexitsforeachdirectionwithasingleerrorflagindicatinganerrorfor  
eitherbyteintheA-to-Bdirectionandaseconderrorflagindicatinganerrorfor  
eitherbyteintheB-to-Adirection. Theparityerrorflagsareopendrainoutputs  
whichcanbetiedtogetherand/ortiedwithflagsfromotherdevicestoformasingle  
errorflagorinterrupt. The parityerrorflags are enabledbythe OExx control  
pins allowing the designer to disable the error flag during combinational  
transitions.  
Thecontrolpins LEAB,CLKAB,andOEAB controloperationintheA-to-B  
directionwhileLEBA,CLKBA,andOEBAcontroltheB-to-Adirection. GEN/  
CHKisonlyfortheselectionofA-to-Boperation. TheB-to-Adirectionisalways  
incheckingmode. TheODD/EVENselectiscommonbetweenthetwodirections.  
Except for the ODD/EVEN control, independent operation can be achieved  
betweenthetwodirectionsbyusingthecorrespondingcontrollines.  
Typical tsk(o) (Output Skew) < 250ps, clocked mode  
Low input and output leakage 1µA (max)  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
VCC = 5V ±10%  
• Balanced Output Drivers:  
– ±24mA(industrial)  
– ±16mA(military)  
• Series current limiting resistors  
• Generate/Check, Check/Check modes  
• Open drain parity error allows wire-OR  
Available in the following packages:  
Industrial: SSOP, TSSOP  
Military: CERPACK  
FUNCTIONALBLOCKDIAGRAM  
LEAB  
CLKAB  
Data  
OEAB  
Parity, data  
B0-15  
16  
18  
PB1,2  
Parity  
Latch/  
Register  
GEN/CHK  
Byte  
2
Parity  
PERB  
Generator/  
Checker  
A0-15  
PA1,2  
(Open Drain)  
ODD/EVEN  
LEBA  
CLKBA  
Parity, Data  
18  
Parity, data  
18  
Latch/  
Register  
OEBA  
Byte  
Parity  
Checking  
PERA  
(Open Drain)  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
MILITARY AND INDUSTRIAL TEMPERATURE RANGES  
SEPTEMBER 2009  
1
© 2009 Integrated Device Technology, Inc.  
DSC-2916/4  

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