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IDT72V801L15TFGI PDF预览

IDT72V801L15TFGI

更新时间: 2024-11-11 13:08:43
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路先进先出芯片时钟
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16页 152K
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IDT72V801L15TFGI 数据手册

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IDT72V801  
IDT72V811  
IDT72V821  
IDT72V831  
IDT72V841  
IDT72V851  
3.3 VOLT DUAL CMOS SyncFIFO™  
DUAL 256 X 9, DUAL 512 X 9,  
DUAL 1,024 X 9, DUAL 2,048 X 9,  
DUAL 4,096 X 9 , DUAL 8,192 X 9  
EachofthetwoFIFOs(designatedFIFOAandFIFOB)containedinthe  
IDT72V801/72V811/72V821/72V831/72V841/72V851hasa9-bitinputdata  
port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8,  
QB0 - QB8).Eachinputportis controlledbya free-runningclock(WCLKA,  
WCLKB), and two Write Enable pins (WENA1, WENA2, WENB1, WENB2).  
DataiswrittenintoeachofthetwoarraysoneveryrisingclockedgeoftheWrite  
Clock (WCLKA, WCLKB) when the appropriate Write Enable pins are  
asserted.  
TheoutputportofeachFIFObankiscontrolledbyitsassociated clockpin  
(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,  
RENB2).TheReadClockcanbetiedtotheWriteClockforsingleclockoperation  
orthetwoclockscanrunasynchronousofoneanotherfordualclockoperation.  
AnOutputEnablepin(OEA,OEB)is providedonthereadportofeachFIFO  
forthree-stateoutputcontrol.  
ꢀEATURES:  
The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs  
The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs  
The IDT72V821 is equivalent to two IDT72V221 1,024 x 9 FIFOs  
The IDT72V831 is equivalent to two IDT72V231 2,048 x 9 FIFOs  
The IDT72V841 is equivalent to two IDT72V241 4,096 x 9 FIFOs  
The IDT72V851 is equivalent to two IDT72V251 8,192 x 9 FIFOs  
Offers optimal combination of large capacity, high speed,  
design flexibility and small footprint  
Ideal for prioritization, bidirectional, and width expansion  
applications  
10 ns read/write cycle time  
5V input tolerant  
Separate control lines and data lines for each FIFO  
Separate Empty, Full, programmable Almost-Empty and  
Almost-Full flags for each FIFO  
Enable puts output data lines in high-impedance state  
Space-saving 64-pin plastic Thin Quad Flat Pack (TQFP/  
STQFP)  
EachofthetwoFIFOshastwofixedflags,Empty(EFA,EFB)andFull(FFA,  
FFB). Twoprogrammableflags,Almost-Empty(PAEA,PAEB)andAlmost-Full  
(PAFA,PAFB),areprovidedforeachFIFObanktoimprovememoryutilization.  
Ifnotprogrammed,theprogrammableflagsdefaulttoEmpty+7forPAEAand  
PAEB, and Full-7 for PAFA and PAFB.  
TheIDT72V801/72V811/72V821/72V831/72V841/72V851architecture  
lendsitselftomanyflexibleconfigurationssuchas:  
Industrial temperature range (–40°C to +85°C) is available  
• 2-levelprioritydatabuffering  
Bidirectionaloperation  
DESCRIPTION:  
TheIDT72V801/72V811/72V821/72V831/72V841/72V851/72V851are  
dualsynchronous(clocked)FIFOs. Thedeviceisfunctionallyequivalentto  
twoIDT72V201/72V211/72V221/72V231/72V241/72V251FIFOsinasingle  
packagewithallassociatedcontrol,data,andflaglinesassignedtoseparate  
pins.  
Widthexpansion  
Depthexpansion  
ThisFIFOisfabricatedusingIDT'shigh-performancesubmicronCMOS  
technology.  
ꢀUNCTIONAL BLOCK DIAGRAM  
EFA  
PAEA  
PAFA  
FFA  
WCLKB  
WCLKA  
WENA1  
WENA2  
WENB1  
DA0 - DA8  
DB0 - DB8  
LDA  
LDB  
WENB2  
INPUT REGISTER  
OFFSET REGISTER  
INPUT REGISTER  
OFFSET REGISTER  
EFB  
FLAG  
LOGIC  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
WRITE CONTROL  
LOGIC  
PAEB  
PAFB  
FFB  
RAM ARRAY  
256 x 9, 512 x 9,  
1,024 x 9, 2,048 x 9,  
4,096 x 9, 8,192 x 9  
RAM ARRAY  
256 x 9, 512 x 9,  
1,024 x 9, 2,048 x 9,  
4,096 x 9, 8,192 x 9  
WRITE POINTER  
READ POINTER  
WRITE POINTER  
READ POINTER  
READ CONTROL  
LOGIC  
READ CONTROL  
LOGIC  
OUTPUT REGISTER  
OUTPUT REGISTER  
RESET LOGIC  
RESET LOGIC  
4093 drw 01  
RCLKB  
RENB1  
RENB2  
RSA  
OEA  
RSB  
RCLKA  
OEB  
QB0 - QB8  
QA0 - QA8  
RENA1  
RENA2  
The IDT logo is a registered trademark and the SyncFIFO is a trademark of Integrated Device Technology, Inc.  
APRIL 2001  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
2001 Integrated Device Technology, Inc.  
DSC-4093/1  

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