Datasheet > IDT72V81

IDT72V81

更新时间： 2024-11-20 23:01:15

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
11页	100K
描述
3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO DUAL 512 x 9, DUAL 1,024 x 9 DUAL 2,048 x 9, DUAL 4,096 X 9

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IDT72V81 数据手册

IDT72V81

IDT72V82

IDT72V83

IDT72V84

IDT72V85

3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO

DUAL 512 x 9, DUAL 1,024 x 9

DUAL 2,048 x 9, DUAL 4,096 X 9

DUAL 8,192 X 9

FEATURES:

DESCRIPTION:

♦

The IDT72V81 is equivalent to two IDT72V01 - 512 x 9 FIFOs

The IDT72V82 is equivalent to two IDT72V02 - 1,024 x 9 FIFOs

The IDT72V83 is equivalent to two IDT72V03 - 2,048 x 9 FIFOs

The IDT72V84 is equivalent to two IDT72V04 - 4,096 x 9 FIFOs

The IDT72V85 is equivalent to two IDT72V05 - 8,192 x 9 FIFOs

Low power consumption

TheIDT72V81/72V82/72V83/72V84/72V85aredual-FIFOmemoriesthat

loadandemptydataonafirst-in/first-outbasis.Thesedevicesarefunctionaland

compatibletotwoIDT72V01/72V02/72V03/72V04/72V05FIFOsinasingle

packagewithallassociatedcontrol,data,andflaglinesassignedtoseparate

pins. The devices use Full and Empty flags to prevent data overflow and

underflowandexpansionlogictoallowforunlimitedexpansioncapabilityinboth

word size and depth.

— Active: 330 mW (max.)

— Power-down: 18 mW (max.)

Ultra high speed—15 ns access time

Asynchronous and simultaneous read and write

Offers optimal combination of data capacity, small foot print

and functional flexibility

The reads and writes are internally sequential through the use of ring

pointers,withnoaddressinformationrequiredtoloadandunloaddata. Data

istoggledinandoutofthedevicesthroughtheuseoftheWrite(W)andRead

(R) pins.

♦

The devices utilize a 9-bit wide data array to allow for control and parity

♦

Ideal for bidirectional, width expansion, depth expansion, bus- bitsattheuser’soption.Thisfeatureis especiallyusefulindatacommunications

matching, and data sorting applications

Status Flags: Empty, Half-Full, Full

Auto-retransmit capability

High-performance CEMOS™ technology

Space-saving TSSOP package

applicationswhereitisnecessarytouseaparitybitfortransmission/reception

errorchecking.ItalsofeaturesaRetransmit(RT)capabilitythatallowsforreset

of the read pointer to its initial position when RT is pulsed low to allow for

retransmissionfromthebeginningofdata.AHalf-FullFlagisavailableinthe

singledevicemodeandwidthexpansionmodes.

These FIFOs are fabricated using IDT’s high-speed CMOS technology.

Theyaredesignedforthoseapplicationsrequiringasynchronousandsimul-

taneousread/writesinmultiprocessingandratebufferapplications.

♦

Industrial temperature range (–40°C to +85°C) is available

FUNCTIONAL BLOCK DIAGRAM

DATA INPUTS

(DA

-DA

RSA

(DB

-DB

RSB

WRITE

CONTROL

WRITE

CONTROL

RAM

ARRAY A

512 x 9

ARRAY A

512 x 9

1,024 x 9

2,048 x 9

4,096 x 9

8,192 x 9

1,024 x 9

2,048 x 9

4,096 x 9

8,192 x 9

WRITE

POINTER

WRITE

POINTER

READ

POINTER

READ

POINTER

THREE-

STATE

BUFFERS

THREE-

STATE

BUFFERS

READ

CONTROL

READ

CONTROL

RESET

LOGIC

RESET

LOGIC

FLAG

LOGIC

FLAG

LOGIC

EXPANSION

LOGIC

EXPANSION

LOGIC

XIA

FFA EFA

XIB

XOA/HFA

FLA/RTA

FFB EFB

FLB/RTB

DATA

XOB/HFB

DATA

OUTPUTS

(QB0-QB8)

OUTPUTS

3966 drw 01

(QA -QA8)

August 1999

1999 Integrated Device Technology, Inc.

DSC-3966/-

12 3 4 5 6 7...11

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与IDT72V81相关器件

型号	品牌	获取价格	描述	数据表
IDT72V81_06	IDT	获取价格	3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO
IDT72V81_09	IDT	获取价格	3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO DUAL 512 x 9, DUAL 1,024 x 9 DUAL 2,048 x 9, DUAL 4,0
IDT72V811	IDT	获取价格	3.3 VOLT DUAL CMOS SyncFIFO⑩
IDT72V811L10PF	IDT	获取价格	3.3 VOLT DUAL CMOS SyncFIFO⑩
IDT72V811L10PF8	IDT	获取价格	FIFO, 512X9, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72V811L10PFG	IDT	获取价格	Bi-Directional FIFO, 512X9, 6.5ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64
IDT72V811L10TF	IDT	获取价格	3.3 VOLT DUAL CMOS SyncFIFO⑩
IDT72V811L10TF8	IDT	获取价格	FIFO, 512X9, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, SLIM, TQFP-64
IDT72V811L10TF9	IDT	获取价格	FIFO, 512X9, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, SLIM, TQFP-64
IDT72V811L15PF	IDT	获取价格	3.3 VOLT DUAL CMOS SyncFIFO⑩

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