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IDT72V3653L15PF8 PDF预览

IDT72V3653L15PF8

更新时间: 2024-11-21 20:02:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
30页 317K
描述
FIFO, 2KX36, 10ns, Synchronous, CMOS, PQFP128, TQFP-128

IDT72V3653L15PF8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP-128针数:128
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.92
最长访问时间:10 ns最大时钟频率 (fCLK):66.7 MHz
周期时间:15 nsJESD-30 代码:R-PQFP-G128
JESD-609代码:e0长度:20 mm
内存密度:73728 bit内存集成电路类型:OTHER FIFO
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:128
字数:2048 words字数代码:2000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2KX36
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP128,.63X.87,20
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.0004 A
子类别:FIFOs最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

IDT72V3653L15PF8 数据手册

 浏览型号IDT72V3653L15PF8的Datasheet PDF文件第2页浏览型号IDT72V3653L15PF8的Datasheet PDF文件第3页浏览型号IDT72V3653L15PF8的Datasheet PDF文件第4页浏览型号IDT72V3653L15PF8的Datasheet PDF文件第5页浏览型号IDT72V3653L15PF8的Datasheet PDF文件第6页浏览型号IDT72V3653L15PF8的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING  
2,048 x 36  
4,096 x 36  
8,192 x 36  
IDT72V3653  
IDT72V3663  
IDT72V3673  
Retransmit Capability  
FEATURES  
Reset clears data and configures FIFO, Partial Reset clears data  
but retains configuration settings  
Mailbox bypass registers for each FIFO  
Free-running CLKA and CLKB may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
Memory storage capacity:  
IDT72V3653  
IDT72V3663  
IDT72V3673  
2,048 x 36  
4,096 x 36  
8,192 x 36  
Clock frequencies up to 100 MHz (6.5 ns access time)  
Clocked FIFO buffering data from Port A to Port B  
IDT Standard timing (using EF and FF) or First Word Fall  
Through Timing (using OR and IR flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has  
five default offsets (8, 16, 64, 256 and 1,024)  
Serial or parallel programming of partial flags  
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits  
(byte)  
Easily expandable in width and depth  
Auto power down minimizes power dissipation  
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
Pin and functionally compatible versions of the 5V operating  
IDT723653/723663/723673  
Pin compatible with the lower density parts, IDT72V3623/  
72V3633/72V3643  
Industrial temperature range (–40°C to +85°C) is available  
Big- or Little-Endian format for word and byte bus sizes  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
Port-A  
W/RA  
Control  
ENA  
Logic  
MBA  
36  
RAM ARRAY  
36  
36  
FIFO1  
Mail1,  
Mail2,  
Reset  
Logic  
2,048 x 36  
4,096 x 36  
8,192 x 36  
RS1  
RS2  
PRS  
36  
RT  
RTM  
FIFO  
Retransmit  
Logic  
Write  
Pointer  
Read  
Pointer  
A0-A35  
B0-B35  
Status Flag  
Logic  
EF/OR  
AE  
FF/IR  
AF  
36  
36  
FS2  
FS0/SD  
FS1/SEN  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
13  
CLKB  
CSB  
W/RB  
ENB  
MBB  
BE  
Port-B  
Control  
Logic  
BM  
SIZE  
Mail 2  
Register  
4662 drw01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
NOVEMBER 2003  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4662/2  

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