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IDT72V3656L15PFG PDF预览

IDT72V3656L15PFG

更新时间: 2024-11-21 15:46:07
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
39页 385K
描述
FIFO, 2KX36, 10ns, Synchronous, CMOS, PQFP128, TQFP-128

IDT72V3656L15PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:128
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.84
最长访问时间:10 ns其他特性:MAIL BOX BYPASS REGISTER
周期时间:15 nsJESD-30 代码:R-PQFP-G128
JESD-609代码:e3长度:20 mm
内存密度:73728 bit内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:128字数:2048 words
字数代码:2000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

IDT72V3656L15PFG 数据手册

 浏览型号IDT72V3656L15PFG的Datasheet PDF文件第2页浏览型号IDT72V3656L15PFG的Datasheet PDF文件第3页浏览型号IDT72V3656L15PFG的Datasheet PDF文件第4页浏览型号IDT72V3656L15PFG的Datasheet PDF文件第5页浏览型号IDT72V3656L15PFG的Datasheet PDF文件第6页浏览型号IDT72V3656L15PFG的Datasheet PDF文件第7页 
3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING  
2,048 x 36 x 2  
4,096 x 36 x 2  
8,192 x 36 x 2  
IDT72V3656  
IDT72V3666  
IDT72V3676  
Serial or parallel programming of partial flags  
FEATURES  
Big- or Little-Endian format for word and byte bus sizes  
Loopback mode on Port A  
Retransmit Capability  
Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
Mailbox bypass registers for each FIFO  
Free-running CLKA, CLKB and CLKC may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
Auto power down minimizes power dissipation  
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
Pin and functionally compatible versions of the 5V parts,  
IDT723656/723666/723676  
Pin compatible to the lower density parts, IDT72V3626/3636/3646  
Industrial temperature range (–40°C to +85°C) is available  
Memory storage capacity:  
IDT72V3656  
IDT72V3666  
IDT72V3676  
2,048 x 36 x 2  
4,096 x 36 x 2  
8,192 x 36 x 2  
Clock frequencies up to 100 MHz (6.5ns access time)  
Two independent FIFOs buffer data between one bidirectional  
36-bit port and two unidirectional 18-bit ports (Port C receives  
and Port B transmits)  
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on  
Ports B and C  
Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag  
functions) or First Word Fall Through Timing (using ORA, ORB,  
IRA, and IRC flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has  
five default offsets (8, 16, 64, 256 and 1,024)  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
CLKA  
CSA  
Register  
Port-A  
Control  
Logic  
18  
W/RA  
B0-B17  
ENA  
RAM ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
MBA  
36  
36  
LOOP  
CLKB  
RENB  
CSB  
Port-B  
Control  
Logic  
FIFO1,  
Mail1  
Reset  
Logic  
MRS1  
PRS1  
MBB  
Read  
Pointer  
Write  
Pointer  
SIZEB  
36  
Status Flag  
Logic  
FFA/IRA  
EFB/ORB  
AFA  
AEB  
FIFO1  
FIFO2  
Common  
Port  
FS2  
FS0/SD  
Control  
Logic  
Programmable Flag  
Offset Registers  
Timing  
Mode  
BE  
FS1/SEN  
(B and C)  
A0-A35  
13  
FWFT  
FFC/IRC  
AFC  
Status Flag  
Logic  
EFA/ORA  
AEA  
Read  
Pointer  
Write  
Pointer  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
36  
RT1  
RTM  
RT2  
FIFO1 and  
FIFO2  
Retransmit  
Logic  
RAM ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
18  
36  
36  
C0-C17  
CLKC  
WENC  
MBC  
Port-C  
Control  
Logic  
Mail 2  
Register  
SIZEC  
4665 drw01  
MBF2  
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc. TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
NOVEMBER 2003  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4665/4  

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