Datasheet > IDT72V3611

IDT72V3611

更新时间： 2024-09-15 05:11:59

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
20页	199K
描述
3.3 VOLT CMOS SyncFIFO 64 x 36

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中文翻译

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数据手册

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IDT72V3611 数据手册

3.3 VOLT CMOS SyncFIFO^TM

64 x 36

IDT72V3611

• Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving

FEATURES:

120-pin Thin Quad Flatpack (PF)

Industrial temperature range (–40°C to +85°C) is available

Pin and functionally compatible version of the 5V operating

IDT723611

• 64 x 36 storage capacity

• Supports clock frequencies up to 67MHz

• Fast access times of 10ns

• Free-running CLKA and CLKB may be asynchronous or

coincident (permits simultaneous reading and writing of

data on a single clock edge)

•

DESCRIPTION:

• Synchronous data buffering from Port A to Port B

• Mailbox bypass register in each direction

• Programmable Almost-Full (AF) and Almost-Empty (AE) flags

• Microprocessor Interface Control Logic

The IDT72V3611 is a pin and functionally compatible version of the

IDT723611, designed to run off a 3.3V supply for exceptionally low power

consumption. This device is a monolithic, high-speed, low-power, CMOS

Synchronous(clocked)FIFOmemorywhichsupportsclockfrequenciesupto

• Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA 67MHzandhasreadaccesstimesasfastas10ns.The64 x 36dual-portFIFO

• Empty Flag (EF) and Almost-Empty (AE) flags synchronized by

CLKB

• Passive parity checking on each Port

• Parity Generation can be selected for each Port

buffers datafromPortAtoPortB.TheFIFOoperates inIDTStandardmode

andhasflagstoindicateemptyandfullconditions,andtwoprogrammableflags,

Almost-Full(AF)andAlmost-Empty(AE),toindicatewhenaselectednumber

ofwordsisstoredinmemory. Communicationbetweeneachportcantakeplace

FUNCTIONAL BLOCK DIAGRAM

CLKA

CSA

W/RA

ENA

Port-A

Control

Logic

MBA

MBF1

PEFB

Parity

Gen/Check

Mail 1

PGB

RST

Reset

Logic

ODD/

EVEN

RAM

ARRAY

64 x 36

- A35

Read

Pointer

Write

Pointer

B0 - B35

Status Flag

Logic

FIFO

Programmable

Flag Offset

Registers

PGA

Mail 2

Parity

Gen/Check

CLKB

CSB

W/RB

ENB

MBB

Port-B

Control

Logic

PEFA

MBF2

4657 drw01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL TEMPERATURE RANGE

MAY 2003

DSC-4657/1

12 3 4 5 6 7...20

中文翻译

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与IDT72V3611相关器件

型号	品牌	获取价格	描述	数据表
IDT72V36110	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC⑩ II 36-BIT FI
IDT72V36110L10BB	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II? 36-BIT FIFO
IDT72V36110L10BBI	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II? 36-BIT FIFO
IDT72V36110L10PF	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC⑩ II 36-BIT FI
IDT72V36110L10PF8	IDT	获取价格	FIFO, 128KX36, 6.5ns, Synchronous, CMOS, PQFP128, PLASTIC, TQFP-128
IDT72V36110L10PF9	IDT	获取价格	FIFO, 128KX36, 6.5ns, Synchronous, CMOS, PQFP128, PLASTIC, TQFP-128
IDT72V36110L10PFG	IDT	获取价格	FIFO, 128KX36, 6.5ns, Synchronous, CMOS, PQFP128, GREEN, PLASTIC, TQFP-128
IDT72V36110L10PFI	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II? 36-BIT FIFO
IDT72V36110L15BB	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II? 36-BIT FIFO
IDT72V36110L15BBI	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II? 36-BIT FIFO

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