5秒后页面跳转
捷配首页

Datasheet > IDT72V36110L7.5PF8
IDT72V36110L7.5PF8 PDF预览

IDT72V36110L7.5PF8

更新时间： 2024-11-06 14:51:27
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
53页 686K
描述
FIFO, 128KX36, 5ns, Synchronous, CMOS, PQFP128, PLASTIC, TQFP-128

阅读下载

中文翻译

获取价格

IDT72V36110L7.5PF8 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：PLASTIC, TQFP-128针数：128
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.63
Is Samacsys：N最长访问时间：5 ns
其他特性：RETRANSMIT; AUTO POWER DOWN; ASYNCHRONOUS MODE IS ALSO POSSIBLE周期时间：7.5 ns
JESD-30 代码：R-PQFP-G128JESD-609代码：e0
长度：20 mm内存密度：4718592 bit
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：128
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX36
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：240认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：14 mmBase Number Matches：1

IDT72V36110L7.5PF8 数据手册

 浏览型号IDT72V36110L7.5PF8的Datasheet PDF文件第2页浏览型号IDT72V36110L7.5PF8的Datasheet PDF文件第3页浏览型号IDT72V36110L7.5PF8的Datasheet PDF文件第4页浏览型号IDT72V36110L7.5PF8的Datasheet PDF文件第5页浏览型号IDT72V36110L7.5PF8的Datasheet PDF文件第6页浏览型号IDT72V36110L7.5PF8的Datasheet PDF文件第7页 
3.3 VOLT HIGH-DENSITY SUPERSYNC II™  
36-BIT FIFO  
65,536 x 36  
131,072 x 36  
IDT72V36100  
IDT72V36110  
• Empty, Full and Half-Full flags signal FIFO status  
FEATURES:  
• Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of eight preselected offsets  
• Selectable synchronous/asynchronous timing modes for Almost-  
Empty and Almost-Full flags  
• Program programmable flags by either serial or parallel means  
• Select IDT Standard timing (using EF and FF flags) or First Word  
Fall Through timing (using OR and IR flags)  
• Output enable puts data outputs into high impedance state  
• Easily expandable in depth and width  
• JTAG port, provided for Boundary Scan function (PBGA Only)  
• Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
• Availableina128-pinThinQuadFlatPack(TQFP)ora144-pinPlastic  
Ball Grid Array (PBGA) (with additional features)  
• Pin compatible to the SuperSync II (IDT72V3640/72V3650/72V3660/  
72V3670/72V3680/72V3690)family  
• High-performance submicron CMOS technology  
• Industrial temperature range (–40°C to +85°C) is available  
• Choose among the following memory organizations:  
IDT72V36100  
IDT72V36110  
65,536 x 36  
131,072 x 36  
• Higher density, 2Meg and 4Meg SuperSync II FIFOs  
• Up to 166 MHz Operation of the Clocks  
• UserselectableAsynchronous readand/orwriteports (PBGAOnly)  
• User selectable input and output port bus-sizing  
- x36 in to x36 out  
- x36 in to x18 out  
- x36 in to x9 out  
- x18 in to x36 out  
- x9 in to x36 out  
• Big-Endian/Little-Endian user selectable byte representation  
• 5V input tolerant  
• Fixed, low first word latency  
• Zero latency retransmit  
• Auto power down minimizes standby power consumption  
• Master Reset clears entire FIFO  
• Partial Reset clears data, but retains programmable settings  
FUNCTIONALBLOCKDIAGRAM  
*Available on the PBGA package only.  
D0 -Dn (x36, x18 or x9)  
LD SEN  
WEN  
WCLK/WR  
*
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
EF/OR  
FLAG  
LOGIC  
PAE  
HF  
FWFT/SI  
PFM  
FSEL0  
FSEL1  
WRITE CONTROL  
LOGIC  
ASYW  
*
RAM ARRAY  
65,536 x 36  
131,072 x 36  
WRITE POINTER  
READ POINTER  
BE  
CONTROL  
LOGIC  
IP  
RT  
RM  
ASYR  
READ  
CONTROL  
LOGIC  
BM  
IW  
OW  
OUTPUT REGISTER  
BUS  
*
CONFIGURATION  
MRS  
PRS  
RESET  
LOGIC  
RCLK/RD  
*
REN  
TCK  
*
*
TRST  
TMS  
TDI  
TDO  
JTAG CONTROL  
(BOUNDARY  
SCAN)  
*
6117 drw01  
*
Q0 -Qn (x36, x18 or x9)  
OE  
*
*
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
IDT and the IDT logo are a registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.  
SEPTEMBER 2003  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6117/10  
1234567...53

中文翻译

下载PDF

与IDT72V36110L7.5PF8相关器件

型号 品牌 获取价格 描述 数据表
IDT72V36110L7.5PFG IDT

获取价格

 		FIFO, 128KX36, 5ns, Synchronous, CMOS, PQFP128, GREEN, PLASTIC, TQFP-128
IDT72V36110L7.5PFGI IDT

获取价格

 		FIFO, 128KX36, 5ns, Synchronous, CMOS, PQFP128, GREEN, PLASTIC, TQFP-128
IDT72V36110L7.5PFI IDT

获取价格

 		3.3 VOLT HIGH-DENSITY SUPERSYNC II? 36-BIT FIFO
IDT72V36110L7-5BB IDT

获取价格

 		FIFO, 128KX36, 5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144
IDT72V36110L7-5BB8 IDT

获取价格

 		FIFO, 128KX36, 5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144
IDT72V36110L7-5BBGI8 IDT

获取价格

 		FIFO, 128KX36, 5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1MM PITCH, GREEN, PLASTIC, BGA
IDT72V36110L7-5BBI IDT

获取价格

 		FIFO, 128KX36, 5ns, Synchronous/Asynchronous, CMOS, PBGA144
IDT72V36110L75PF IDT

获取价格

 		3.3 VOLT HIGH-DENSITY SUPERSYNC⑩ II 36-BIT FI
IDT72V36110L7-5PF IDT

获取价格

 		FIFO, 128KX36, 5ns, Synchronous, CMOS, PQFP128, PLASTIC, TQFP-128
IDT72V36110L7-5PF9 IDT

获取价格

 		FIFO, 128KX36, 5ns, Synchronous, CMOS, PQFP128, PLASTIC, TQFP-128

与IDT72V36110L7.5PF8相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证