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IDT72V36110L7-5BBI PDF预览

IDT72V36110L7-5BBI

更新时间: 2024-11-06 19:31:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
48页 466K
描述
FIFO, 128KX36, 5ns, Synchronous/Asynchronous, CMOS, PBGA144

IDT72V36110L7-5BBI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active包装说明:BGA, BGA144,12X12,40
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.23
最长访问时间:5 ns最大时钟频率 (fCLK):133.3 MHz
JESD-30 代码:S-PBGA-B144JESD-609代码:e0
内存密度:4718592 bit内存集成电路类型:OTHER FIFO
内存宽度:36湿度敏感等级:3
端子数量:144字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS/ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX36封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA144,12X12,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified最大待机电流:0.015 A
子类别:FIFOs最大压摆率:0.04 mA
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30Base Number Matches:1

IDT72V36110L7-5BBI 数据手册

 浏览型号IDT72V36110L7-5BBI的Datasheet PDF文件第2页浏览型号IDT72V36110L7-5BBI的Datasheet PDF文件第3页浏览型号IDT72V36110L7-5BBI的Datasheet PDF文件第4页浏览型号IDT72V36110L7-5BBI的Datasheet PDF文件第5页浏览型号IDT72V36110L7-5BBI的Datasheet PDF文件第6页浏览型号IDT72V36110L7-5BBI的Datasheet PDF文件第7页 
3.3 VOLT HIGH-DENSITY SUPERSYNC II™  
36-BIT FIFO  
65,536 x 36  
131,072 x 36  
IDT72V36100  
IDT72V36110  
Empty, Full and Half-Full flags signal FIFO status  
FEATURES:  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of eight preselected offsets  
Selectable synchronous/asynchronous timing modes for Almost-  
Empty and Almost-Full flags  
Program programmable flags by either serial or parallel means  
Select IDT Standard timing (using EF and FF flags) or First Word  
Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
JTAG port, provided for Boundary Scan function (PBGA Only)  
Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
Availableina128-pinThinQuadFlatPack(TQFP)ora144-pinPlastic  
Ball Grid Array (PBGA) (with additional features)  
Pin compatible to the SuperSync II (IDT72V3640/72V3650/72V3660/  
72V3670/72V3680/72V3690)family  
High-performance submicron CMOS technology  
Industrial temperature range (–40°C to +85°C) is available  
Choose among the following memory organizations:  
IDT72V36100  
IDT72V36110  
65,536 x 36  
131,072 x 36  
Higher density, 2Meg and 4Meg SuperSync II FIFOs  
Up to 166 MHz Operation of the Clocks  
UserselectableAsynchronous readand/orwriteports (PBGAOnly)  
User selectable input and output port bus-sizing  
- x36 in to x36 out  
- x36 in to x18 out  
- x36 in to x9 out  
- x18 in to x36 out  
- x9 in to x36 out  
Big-Endian/Little-Endian user selectable byte representation  
5V input tolerant  
Fixed, low first word latency  
Zero latency retransmit  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
Partial Reset clears data, but retains programmable settings  
FUNCTIONALBLOCKDIAGRAM  
*Available on the PBGA package only.  
D0 -Dn (x36, x18 or x9)  
LD SEN  
WEN  
WCLK/WR  
*
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
EF/OR  
FLAG  
LOGIC  
PAE  
HF  
FWFT/SI  
PFM  
FSEL0  
FSEL1  
WRITE CONTROL  
LOGIC  
ASYW  
*
RAM ARRAY  
65,536 x 36  
131,072 x 36  
WRITE POINTER  
READ POINTER  
BE  
CONTROL  
LOGIC  
IP  
RT  
RM  
ASYR  
READ  
CONTROL  
LOGIC  
BM  
IW  
OW  
OUTPUT REGISTER  
BUS  
*
CONFIGURATION  
MRS  
PRS  
RESET  
LOGIC  
RCLK/RD  
*
REN  
TCK  
*
*
TRST  
TMS  
TDI  
TDO  
JTAG CONTROL  
(BOUNDARY  
SCAN)  
*
6117 drw01  
*
Q0 -Qn (x36, x18 or x9)  
OE  
*
*
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
IDT and the IDT logo are a registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.  
SEPTEMBER 2003  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6117/10  

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