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IDT72V36106L15PFG8 PDF预览

IDT72V36106L15PFG8

更新时间: 2024-09-15 15:43:35
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
39页 389K
描述
FIFO, 64KX36, 10ns, Synchronous, CMOS, PQFP128, TQFP-128

IDT72V36106L15PFG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP-128针数:128
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.84
最长访问时间:10 ns周期时间:15 ns
JESD-30 代码:R-PQFP-G128JESD-609代码:e3
长度:20 mm内存密度:2359296 bit
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:128
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX36
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

IDT72V36106L15PFG8 数据手册

 浏览型号IDT72V36106L15PFG8的Datasheet PDF文件第2页浏览型号IDT72V36106L15PFG8的Datasheet PDF文件第3页浏览型号IDT72V36106L15PFG8的Datasheet PDF文件第4页浏览型号IDT72V36106L15PFG8的Datasheet PDF文件第5页浏览型号IDT72V36106L15PFG8的Datasheet PDF文件第6页浏览型号IDT72V36106L15PFG8的Datasheet PDF文件第7页 
3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING  
16,384 x 36 x 2  
32,768 x 36 x 2  
65,536 x 36 x 2  
IDT72V3686  
IDT72V3696  
IDT72V36106  
Serial or parallel programming of partial flags  
FEATURES  
Big- or Little-Endian format for word and byte bus sizes  
Loopback mode on Port A  
Retransmit Capability  
Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
Mailbox bypass registers for each FIFO  
Free-running CLKA, CLKB and CLKC may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
Auto power down minimizes power dissipation  
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
Pin compatible to the lower density parts, IDT72V3626/72V3636/  
72V3646/72V3656/72V3666/72V3676  
Memory storage capacity:  
IDT72V3686 – 16,384 x 36 x 2  
IDT72V3696 – 32,768 x 36 x 2  
IDT72V36106 – 65,536 x 36 x 2  
Clock frequencies up to 100 MHz (6.5ns access time)  
Two independent FIFOs buffer data between one bidirectional  
36-bit port and two unidirectional 18-bit ports (Port C receives  
and Port B transmits)  
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on  
Ports B and C  
Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag  
functions) or First Word Fall Through Timing (using ORA, ORB,  
IRA, and IRC flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has  
five default offsets (8, 16, 64, 256 and 1024)  
Industrial temperature range (–40°C to +85°C) is available  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
Port-A  
Control  
Logic  
18  
W/RA  
ENA  
B0-B17  
RAM ARRAY  
16,384 x 36  
32,768 x 36  
65,536 x 36  
MBA  
36  
36  
LOOP  
CLKB  
RENB  
CSB  
Port-B  
Control  
Logic  
FIFO1,  
Mail1  
Reset  
Logic  
MRS1  
PRS1  
MBB  
Read  
Pointer  
Write  
Pointer  
SIZEB  
36  
Status Flag  
Logic  
FFA/IRA  
EFB/ORB  
AFA  
AEB  
FIFO1  
FIFO2  
Common  
Port  
FS2  
FS0/SD  
Control  
Logic  
Programmable Flag  
Offset Registers  
Timing  
Mode  
BE  
FS1/SEN  
(B and C)  
A0-A35  
16  
FWFT  
FFC/IRC  
AFC  
Status Flag  
Logic  
EFA/ORA  
AEA  
Read  
Pointer  
Write  
Pointer  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
36  
RT1  
RTM  
RT2  
FIFO1 and  
FIFO2  
Retransmit  
Logic  
RAM ARRAY  
16,384 x 36  
32,768 x 36  
65,536 x 36  
18  
36  
36  
C0-C17  
CLKC  
WENC  
MBC  
Port-C  
Control  
Logic  
Mail 2  
Register  
SIZEC  
4676 drw01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERICAL TEMPERATURE RANGE  
NOVEMBER 2003  
1
DSC-4676/4  
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  

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