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IDT72T51343L5BBI

更新时间： 2024-11-12 05:11:59
品牌 Logo 应用领域
艾迪悌 - IDT 控制器
页数 文件大小 规格书
55页 521K
描述
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits

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IDT72T51343L5BBI 数据手册

 浏览型号IDT72T51343L5BBI的Datasheet PDF文件第2页浏览型号IDT72T51343L5BBI的Datasheet PDF文件第3页浏览型号IDT72T51343L5BBI的Datasheet PDF文件第4页浏览型号IDT72T51343L5BBI的Datasheet PDF文件第5页浏览型号IDT72T51343L5BBI的Datasheet PDF文件第6页浏览型号IDT72T51343L5BBI的Datasheet PDF文件第7页 
ADVANCE INFORMATION  
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES  
(8 QUEUES) 18 BIT WIDE CONFIGURATION  
589,824 bits, 1,179,648 bits and 2,359,296 bits  
IDT72T51333  
IDT72T51343  
IDT72T51353  
•
•
•
•
Individual, Active queue flags (OV, FF, PAE, PAF)  
8 bit parallel flag status on both read and write ports  
Provides continuous PAE and PAF status of up to 8 Queues  
Global Bus Matching - (All Queues have same Input Bus Width  
and Output Bus Width)  
User Selectable Bus Matching Options:  
- x18in to x18out  
- x9in to x18out  
FEATURES:  
•
Choose from among the following memory density options:  
IDT72T51333  
IDT72T51343  
IDT72T51353  
Total Available Memory = 589,824 bits  
Total Available Memory = 1,179,648 bits  
Total Available Memory = 2,359,296 bits  
•
•
•
Configurable from 1 to 8 Queues  
Queues may be configured at master reset from the pool of  
Total Available Memory in blocks of 512 x 18 or 1,024 x 9  
Independent Read and Write access per queue  
User programmable via serial port  
User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL  
Default multi-queue device configurations  
-IDT72T51333: 4,096 x 18 x 8Q  
- x18in to x9out  
- x9in to x9out  
•
•
•
•
•
•
•
•
FWFT mode of operation on read port  
Partial Reset, clears data in single Queue  
Expansion of up to 8 multi-queue devices in parallel is available  
Power Down Input provides additional power savings in HSTL  
and eHSTL modes.  
JTAG Functionality (Boundary Scan)  
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm  
HIGH Performance submicron CMOS technology  
-IDT72T51343: 8,192 x 18 x 8Q  
-IDT72T51353: 16,384 x 18 x 8Q  
•
•
•
•
•
•
•
100% Bus Utilization, Read and Write on every clock cycle  
200 MHz High speed operation (5ns cycle time)  
3.6ns access time  
Echo Read Enable & Echo Read Clock Outputs  
FUNCTIONALBLOCKDIAGRAM  
MULTI-QUEUE FLOW-CONTROL DEVICE  
RADEN  
ESTR  
WADEN  
FSTR  
RDADD  
6
WRADD  
WEN  
Q0  
REN  
6
RCLK  
EREN  
WCLK  
ERCLK  
OE  
Q
out  
x9, x18  
D
in  
x9, x18  
DATA IN  
DATA OUT  
OV  
FF  
Q7  
PAF  
PAFn  
PAE  
PAEn  
8
8
6113 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc  
NOVEMBER 2003  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6113/2  
1234567...55

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与IDT72T51343L5BBI相关器件

型号 品牌 获取价格 描述 数据表
IDT72T51343L6BB IDT

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 		2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1
IDT72T51343L6BB8 IDT

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 		FIFO, 64KX18, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT72T51343L6BBI IDT

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 		2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1
IDT72T51353 IDT

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 		2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1
IDT72T51353L5BB IDT

获取价格

 		2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1
IDT72T51353L5BBI IDT

获取价格

 		2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1
IDT72T51353L6BB IDT

获取价格

 		2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1
IDT72T51353L6BB8 IDT

获取价格

 		FIFO, 128KX18, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT72T51353L6BBI IDT

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 		2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1
IDT72T51353L7-5BB IDT

获取价格

 		FIFO, 128KX18, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256

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