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IDT72T51353L7-5BBI PDF预览

IDT72T51353L7-5BBI

更新时间: 2024-11-12 15:34:47
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
11页 202K
描述
FIFO, 128KX18, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256

IDT72T51353L7-5BBI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:256
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.92
周期时间:7.5 nsJESD-30 代码:S-PBGA-B256
JESD-609代码:e0长度:17 mm
内存密度:2359296 bit内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:256字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX18可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):225
认证状态:Not Qualified座面最大高度:3.5 mm
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:20宽度:17 mm
Base Number Matches:1

IDT72T51353L7-5BBI 数据手册

 浏览型号IDT72T51353L7-5BBI的Datasheet PDF文件第2页浏览型号IDT72T51353L7-5BBI的Datasheet PDF文件第3页浏览型号IDT72T51353L7-5BBI的Datasheet PDF文件第4页浏览型号IDT72T51353L7-5BBI的Datasheet PDF文件第5页浏览型号IDT72T51353L7-5BBI的Datasheet PDF文件第6页浏览型号IDT72T51353L7-5BBI的Datasheet PDF文件第7页 
ADVANCE INFORMATION  
IDT72T51333  
2.5V MULTI-QUEUE FIFO (8 QUEUES)  
18 BIT WIDE CONFIGURATION  
589,824 bits, 1,179,648 bits and  
2,359,296 bits  
IDT72T51343  
IDT72T51353  
Individual, Active queue flags (OV, FF, PAE, PAF, PR)  
8 bit parallel flag status on both read and write ports  
Provides continuous PAE and PAF status of up to 8 Queues  
Global Bus Matching - (All Queues have same Input Bus Width  
and Output Bus Width)  
User Selectable Bus Matching Options:  
- x18in to x18out  
- x9in to x18out  
FEATURES:  
Choose from among the following memory density options:  
IDT72T51333  
IDT72T51343  
IDT72T51353  
Total Available Memory = 589,824 bits  
Total Available Memory = 1,179,648 bits  
Total Available Memory = 2,359,296 bits  
Configurable from 1 to 8 Queues  
Queues may be configured at master reset from the pool of  
Total Available Memory in blocks of 512 x 18 or 1,024 x 9  
Independent Read and Write access per queue  
User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL  
User programmable via serial port  
- x18in to x9out  
- x9in to x9out  
FWFT mode of operation on read port  
Packet Ready mode of operation  
Partial Reset, clears data in single Queue  
Expansion of up to 8 Multi-Queue devices in parallel is available  
Power Down Input provides additional power savings in HSTL  
and eHSTL modes.  
JTAG Functionality (Boundary Scan)  
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm  
HIGH Performance submicron CMOS technology  
Default Multi-Queue device configurations  
-IDT72T51333: 4,096 x 18 x 8Q  
-IDT72T51343: 8,192 x 18 x 8Q  
-IDT72T51353: 16,384 x 18 x 8Q  
100% Bus Utilization, Read and Write on every clock cycle  
200 MHz High speed operation (5ns cycle time)  
3.6ns access time  
Echo Read Enable & Echo Read Clock Outputs  
DATA PATH FLOW DIAGRAM  
MULTI-QUEUE FIFO  
RADEN  
ESTR  
WADEN  
FSTR  
RDADD  
7
WRADD  
Q0  
REN  
6
RCLK  
EREN  
WEN  
WCLK  
ERCLK  
OE  
Q
D
in  
out  
x9, x18  
x9, x18  
DATA OUT  
DATA IN  
OV  
FF  
Qmax  
PAF  
PAE  
PAFn  
PAEn  
8
8
6113 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.  
OCTOBER 2, 2001  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6113/-  

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