Datasheet > IDT72T51553

IDT72T51553

更新时间： 2024-11-12 04:01:19

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
57页	539K
描述
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION

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IDT72T51553 数据手册

ADVANCE INFORMATION

2.5V MULTI-QUEUE FLOW-CONTROL DEVICES

(32 QUEUES) 18 BIT WIDE CONFIGURATION

1,179,648 bits and 2,359,296 bits

IDT72T51543

IDT72T51553

•

Shows PAE and PAF status of 8 Queues

Direct or polled operation of flag status bus

Global Bus Matching - (All Queues have same Input Bus Width

and Output Bus Width)

User Selectable Bus Matching Options:

– x18in to x18out

– x9in to x18out

FEATURES:

•

Choose from among the following memory density options:

IDT72T51543

IDT72T51553

Configurable from 1 to 32 Queues



Total Available Memory = 1,179,648 bits

Total Available Memory = 2,359,296 bits

•

Queues may be configured at master reset from the pool of

Total Available Memory in blocks of 512 x 18 or 1,024 x 9

Independent Read and Write access per queue

User programmable via serial port

User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL

Default multi-queue device configurations

– IDT72T51543 : 2,048 x 18 x 32Q

– x18in to x9out

– x9in to x9out

•

FWFT mode of operation on read port

Partial Reset, clears data in single Queue

Expansion of up to 8 multi-queue devices in parallel is available

Power Down Input provides additional power savings in HSTL

and eHSTL modes.

JTAG Functionality (Boundary Scan)

Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm

HIGH Performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

– IDT72T51553 : 4,096 x 18 x 32Q

•

100% Bus Utilization, Read and Write on every clock cycle

200 MHz High speed operation (5ns cycle time)

3.6ns access time

Echo Read Enable & Echo Read Clock Outputs

Individual, Active queue flags (OV, FF, PAE, PAF)

8 bit parallel flag status on both read and write ports

•

FUNCTIONALBLOCKDIAGRAM

MULTI-QUEUE FLOW-CONTROL DEVICE

RADEN

ESTR

WADEN

FSTR

RDADD

WRADD

REN

RCLK

WEN

EREN

WCLK

ERCLK

out

x9, x18

DATA IN

DATA OUT

PAF

PAFn

PAE

PAEn

Q31

5999 drw01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc

NOVEMBER 2003

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-5999/3

12 3 4 5 6 7...57

中文翻译

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与IDT72T51553相关器件

型号	品牌	获取价格	描述	数据表
IDT72T51553L5BB	IDT	获取价格	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L5BB8	IDT	获取价格	FIFO, 128KX18, 3.6ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT72T51553L5BBI	IDT	获取价格	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L6BB	IDT	获取价格	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L6BB8	IDT	获取价格	FIFO, 128KX18, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT72T51553L6BBI	IDT	获取价格	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L7-5BBI	IDT	获取价格	FIFO, 128KX18, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT72T51556	IDT	获取价格	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits
IDT72T51556L5BB	IDT	获取价格	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits
IDT72T51556L5BB8	IDT	获取价格	FIFO, 64KX36, 3.6ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256

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