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IDT71V65902S80BG8

更新时间： 2024-09-19 14:51:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
26页 947K
描述
ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

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IDT71V65902S80BG8 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, PLASTIC, BGA-119
针数：119Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92Is Samacsys：N
最长访问时间：8 ns其他特性：FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：95 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
长度：22 mm内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：119字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5,3.3 V
认证状态：Not Qualified座面最大高度：2.36 mm
最大待机电流：0.04 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.25 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn63Pb37)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

IDT71V65902S80BG8 数据手册

 浏览型号IDT71V65902S80BG8的Datasheet PDF文件第2页浏览型号IDT71V65902S80BG8的Datasheet PDF文件第3页浏览型号IDT71V65902S80BG8的Datasheet PDF文件第4页浏览型号IDT71V65902S80BG8的Datasheet PDF文件第5页浏览型号IDT71V65902S80BG8的Datasheet PDF文件第6页浏览型号IDT71V65902S80BG8的Datasheet PDF文件第7页 
256K x 36, 512K x 18  
IDT71V65702  
IDT71V65902  
3.3VSynchronousZBT™SRAMs  
2.5V I/O, Burst Counter  
Flow-ThroughOutputs  
Features  
◆
256K x 36, 512K x 18 memory configurations  
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
occurs,beitreadorwrite.  
◆
◆
◆
TheIDT71V65702/5902containaddress,data-inandcontrolsignal  
registers.Theoutputsareflow-through(nooutputdataregister).Output  
enable is the only asynchronous signal and can be used to disable the  
outputsatanygiventime.  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1-BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
2.5V (±5%) I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA).  
AClockEnable(CEN)pinallowsoperationoftheIDT71V65702/5902  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored  
whenCENishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite  
isinitiated.  
TheIDT71V65702/5902haveanon-chipburstcounter.Intheburst  
mode,theIDT71V65702/5902canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
TheIDT71V65702/5902SRAMsutilizeIDT’slatesthigh-performance  
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm  
100-pin plasticthinquadflatpack(TQFP)aswellasa119 ballgridarray  
(BGA) and 165 fine pitch ball grid array (fBGA).  
◆
◆
◆
◆
◆
◆
◆
◆
Description  
The IDT71V65702/5902 are 3.3V high-speed 9,437,184-bit  
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x  
18.Theyaredesignedtoeliminatedeadbuscycleswhenturningthe  
busaroundbetweenreadsandwrites,orwritesandreads.Thusthey  
TM  
havebeengiventhenameZBT ,orZeroBusTurnaround.  
AddressandcontrolsignalsareappliedtotheSRAMduringone  
clock cycle, and on the next clock cycle the associated data cycle  
PinDescriptionSummary  
0
18  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/ O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
1
2
2
CE , CE , CE  
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
1
2
3
4
Individual Byte Write Selects  
Clock  
BW , BW , BW , BW  
CLK  
ADV/LD  
Advance Burst Address/Load New Address  
Linear/Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
LBO  
ZZ  
Asynchronous  
Synchronous  
Static  
I/ O0-I/O31, I/OP1-I/OP4  
Data Input/Output  
Co re Powe r, I/O Powe r  
Ground  
DD DDQ  
V
, V  
Supply  
Supply  
SS  
V
Static  
5315 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
OCTOBER 2004  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-5315/08  
1234567...26

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与IDT71V65902S80BG8相关器件

型号 品牌 获取价格 描述 数据表
IDT71V65902S80BGG IDT

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 		ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65902S80BGGI IDT

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 		ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65902S80BGI IDT

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 		ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65902S80BQ IDT

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 		ZBT SRAM, 512KX18, 8ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65902S80BQGI IDT

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 		ZBT SRAM, 512KX18, 8ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65902S80PFG IDT

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 		ZBT SRAM, 512KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V65902S80PFGI IDT

获取价格

 		ZBT SRAM, 512KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V65902S85B IDT

获取价格

 		ZBT SRAM, 512KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65902S85BGG IDT

获取价格

 		ZBT SRAM, 512KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65902S85BGGI IDT

获取价格

 		ZBT SRAM, 512KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

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