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IDT71V65902S85BGG PDF预览

IDT71V65902S85BGG

更新时间： 2024-11-04 15:42:19
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
26页 949K
描述
ZBT SRAM, 512KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

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IDT71V65902S85BGG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：14 X 22 MM, PLASTIC, BGA-119针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
最长访问时间：8.5 ns其他特性：FLOW-THROUGH ARCHITECTURE
JESD-30 代码：R-PBGA-B119JESD-609代码：e1
长度：22 mm内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：119字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX18封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：2.36 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN SILVER COPPER
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

IDT71V65902S85BGG 数据手册

 浏览型号IDT71V65902S85BGG的Datasheet PDF文件第2页浏览型号IDT71V65902S85BGG的Datasheet PDF文件第3页浏览型号IDT71V65902S85BGG的Datasheet PDF文件第4页浏览型号IDT71V65902S85BGG的Datasheet PDF文件第5页浏览型号IDT71V65902S85BGG的Datasheet PDF文件第6页浏览型号IDT71V65902S85BGG的Datasheet PDF文件第7页 
256K x 36, 512K x 18  
IDT71V65702  
IDT71V65902  
3.3VSynchronousZBT™SRAMs  
2.5V I/O, Burst Counter  
Flow-ThroughOutputs  
Features  
◆
256K x 36, 512K x 18 memory configurations  
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
occurs,beitreadorwrite.  
◆
◆
◆
TheIDT71V65702/5902containaddress,data-inandcontrolsignal  
registers.Theoutputsareflow-through(nooutputdataregister).Output  
enable is the only asynchronous signal and can be used to disable the  
outputsatanygiventime.  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1-BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
2.5V (±5%) I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA).  
AClockEnable(CEN)pinallowsoperationoftheIDT71V65702/5902  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored  
whenCENishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite  
isinitiated.  
TheIDT71V65702/5902haveanon-chipburstcounter.Intheburst  
mode,theIDT71V65702/5902canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
TheIDT71V65702/5902SRAMsutilizeIDT’slatesthigh-performance  
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm  
100-pin plasticthinquadflatpack(TQFP)aswellasa119 ballgridarray  
(BGA) and 165 fine pitch ball grid array (fBGA).  
◆
◆
◆
◆
◆
◆
◆
◆
Description  
The IDT71V65702/5902 are 3.3V high-speed 9,437,184-bit  
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x  
18.Theyaredesignedtoeliminatedeadbuscycleswhenturningthe  
busaroundbetweenreadsandwrites,orwritesandreads.Thusthey  
TM  
havebeengiventhenameZBT ,orZeroBusTurnaround.  
AddressandcontrolsignalsareappliedtotheSRAMduringone  
clock cycle, and on the next clock cycle the associated data cycle  
PinDescriptionSummary  
0
18  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/ O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
1
2
2
CE , CE , CE  
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
1
2
3
4
Individual Byte Write Selects  
Clock  
BW , BW , BW , BW  
CLK  
ADV/LD  
Advance Burst Address/Load New Address  
Linear/Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
LBO  
ZZ  
Asynchronous  
Synchronous  
Static  
I/ O0-I/O31, I/OP1-I/OP4  
Data Input/Output  
Co re Powe r, I/O Powe r  
Ground  
DD DDQ  
V
, V  
Supply  
Supply  
SS  
V
Static  
5315 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
OCTOBER 2004  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-5315/08  
1234567...26

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与IDT71V65902S85BGG相关器件

型号 品牌 获取价格 描述 数据表
IDT71V65902S85BGGI IDT

获取价格

 		ZBT SRAM, 512KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65902S85BGI IDT

获取价格

 		ZBT SRAM, 512KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65902S85BQG IDT

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 		ZBT SRAM, 512KX18, 8.5ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65902S85BQGI IDT

获取价格

 		ZBT SRAM, 512KX18, 8.5ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65902S85PFG IDT

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 		ZBT SRAM, 512KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V65902S85PFGI IDT

获取价格

 		ZBT SRAM, 512KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V65903 IDT

获取价格

 		256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs
IDT71V6590375BGG IDT

获取价格

 		3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6590375BGG8 IDT

获取价格

 		3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs
IDT71V6590375BGGI IDT

获取价格

 		3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

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