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IDT71V6590375BQG

更新时间： 2024-11-05 00:23:19
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艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
23页 615K
描述
3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs

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IDT71V6590375BQG 数据手册

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256K x 36, 512K x 18  
IDT71V65703  
IDT71V65903  
3.3VSynchronousZBT™SRAMs  
3.3V I/O, Burst Counter  
Flow-Through Outputs  
Features  
256K x 36, 512K x 18 memory configurations  
Address and control signals are applied to the SRAM during one  
clock cycle, and on the next clock cycle the associated data cycle  
occurs, be it read or write.  
The IDT71V65703/5903 contain address, data-in and control  
signal registers. The outputs are flow-through (no output data  
register). Output enable is the only asynchronous signal and can be  
used to disable the outputs at any given time.  
A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen  
CEN is high and the internal device registers will hold their previous values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
user to deselect the device when desired. If any one of these three  
is not asserted when ADV/LD is low, no new memory operation can  
be initiated. However, any pending data transfers (reads or writes)  
will be completed. The data bus will tri-state one cycle after the chip  
is deselected or a write is initiated.  
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply ( 5%)  
3.3V ( 5%) I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad  
TheIDT71V65703/5903haveanon-chipburstcounter.Intheburst  
mode,theIDT71V65703/5903canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
The IDT71V65703/5903 SRAMs utilize a high-performance CMOS  
process and are packaged in a JEDEC Standard 14mm x 20mm 100-  
pin plasticthinquadflatpack(TQFP), 119 ballgridarray(BGA) and a 165  
fine pitch ball grid array (fBGA).  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
Green parts available, see ordering information  
Description  
The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit  
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.  
They are designed to eliminate dead bus cycles when turning the bus  
aroundbetweenreadsandwrites, orwritesandreads. Thustheyhave  
been given the name ZBTTM, or Zero Bus Turnaround.  
Pin Description Summary  
A
0
-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE , CE  
1
2, CE2  
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
BW , BW  
CLK  
Individual Byte Write Selects  
Clock  
1
2, BW3, BW4  
ADV/LD  
Advance Burst Address/Load New Address  
Linear/Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
LBO  
ZZ  
Asynchronous  
Synchronous  
Static  
I/O  
0-I/O31 , I/OP1-I/OP4  
Data Input/Output  
Core Power, I/O Power  
Ground  
V
V
DD, VDDQ  
SS  
Supply  
Supply  
Static  
5298 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
OCTOBER 2014  
1
©2014 Integrated Device Technology, Inc.  
DSC-5298/05  
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