Datasheet > IDT71V658S200PF

IDT71V658S200PF

更新时间： 2024-11-04 19:23:23

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
24页	318K
描述
ZBT SRAM, 512KX18, 3.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

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技术参数
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IDT71V658S200PF 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	14 X 20 MM, PLASTIC, TQFP-100	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.86
最长访问时间：	3.2 ns	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
内存密度：	9437184 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	100
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	512KX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	240
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	14 mm
Base Number Matches：	1

IDT71V658S200PF 数据手册

256K x 36, 512K x 18

3.3V Synchronous ZBT™ SRAMs

Smart ZBT™ Feature

2.5V or 3.3V I/O, Burst Counter

PipelinedOutputs

Preliminary

IDT71V656

IDT71V658

Description

Features

◆

The IDT71V656/58 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs. They are designed to eliminate

dead bus cycles when turning the bus around between reads and

writes, or writes and reads. Thus, they have been given the name

256K x 36, 512K x 18 memory configurations

◆

Supports high performance system speed - 200 MHz

(3.2 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

ZBT , or Zero Bus Turnaround.

cycles

◆

Smart ZBT^TMFeature - Eases system timing requirements

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andtwocycleslatertheassociateddatacycleoccurs,beitread

or write.

and reduces the likelihood of bus contention

With Smart ZBT^TMthe output turn-on (tCLZ) is adaptable to

◆

The IDT71V656/58 offer the user an optional Smart functionality

whichsimplifiessystemtimingrequirementswhenturningthebusaround

between writes and reads. Traditionally, SRAMs are designed with

fast turn-on times (tCLZ) in order to meet the requirements of high

speed applications. This fast turn-on may lead to bus contention at

slower speeds, i.e. 133 MHz and slower, since these designs

oftentimes use less aggressive ASICs/controllers with loose turn-off

parameters (tCHZ). Thus at slower speeds, more margin on the

RAM’s tCLZ may be needed to compensate for the slow turn-off of the

ASIC/controller. The IDT71V656/58 have the ability to provide this

extra margin by allowing tCLZ to adapt to the user’s system.

WiththeSmartZBT^TMfeature,theoutputturn-ontime(tCLZ)adaptsto

the user’s system and is solely a function of cycle time (tCYC). Thus

the user's system and is a function of the cycle time.

◆

Backward compatable with IDT’s existing ZBT offerings.

◆

User selectable Smart ZBT^TMor Original ZBT^TMmode pin (MS)

◆

Internally synchronized output buffer enable eliminates the

need to control OE

◆

Single R/W (READ/WRITE) control pin

◆

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

User selectable 3.3V or 2.5V I/O Supply (VDDQ)

Packaged in a JEDEC standard 100-lead plastic thin quad

◆

with Smart ZBT , tCLZ is independent of process, voltage, and

temperature variations. With this deterministic output turn-on fea-

flatpack (TQFP) and 119-lead ball grid array (BGA).

PinDescriptionSummary

A -A

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE , CE , CE

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW , BW , BW , BW

CLK

ADV/LD

Advance burst address / Load new address

Linear / Interleaved Burst Order

Data Input / Output

Core Power, I/O Power

Ground

Synchronous

Static

LBO

I/O -I/O , I/O -I/O

Synchronous

Static

DD DDQ

V , V

Supply

Input

Static

Smart ZBT™ Mode Enable

Static

5000 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

Smart ZBT and Smart Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is also supported by Micron Technology, Inc.

OCTOBER 1999

DSC-5000/04

12 3 4 5 6 7...24

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与IDT71V658S200PF相关器件

型号	品牌	获取价格	描述	数据表
IDT71V65902	ETC	获取价格	256K x 36, 512K x 18 3.3V Synchronous ZB TM SRAMs 2.5V I/O, Burst Counter Flow-Through Out
IDT71V65902S75BQ	IDT	获取价格	ZBT SRAM, 512KX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65902S75BQG	IDT	获取价格	ZBT SRAM, 512KX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65902S80BG	IDT	获取价格	ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65902S80BG8	IDT	获取价格	ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65902S80BGG	IDT	获取价格	ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65902S80BGGI	IDT	获取价格	ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65902S80BGI	IDT	获取价格	ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V65902S80BQ	IDT	获取价格	ZBT SRAM, 512KX18, 8ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65902S80BQGI	IDT	获取价格	ZBT SRAM, 512KX18, 8ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165

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