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IDT71V65902 PDF预览

IDT71V65902

更新时间: 2024-11-04 05:39:07
品牌 Logo 应用领域
其他 - ETC 计数器静态存储器
页数 文件大小 规格书
26页 495K
描述
256K x 36, 512K x 18 3.3V Synchronous ZB TM SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs

IDT71V65902 数据手册

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256K x 36, 512K x 18  
IDT71V65702  
IDT71V65902  
3.3VSynchronousZBTSRAMs  
2.5V I/O, Burst Counter  
Flow-ThroughOutputs  
Features  
256K x 36, 512K x 18 memory configurations  
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
occurs,beitreadorwrite.  
TheIDT71V65702/5902containaddress,data-inandcontrolsignal  
registers.Theoutputsareflow-through(nooutputdataregister).Output  
enable is the only asynchronous signal and can be used to disable the  
outputsatanygiventime.  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1-BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
2.5V (±5%) I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA).  
AClockEnable(CEN)pinallowsoperationoftheIDT71V65702/5902  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored  
whenCENishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite  
isinitiated.  
TheIDT71V65702/5902haveanon-chipburstcounter.Intheburst  
mode,theIDT71V65702/5902canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
TheIDT71V65702/5902SRAMsutilizeIDT’slatesthigh-performance  
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm  
100-pin plasticthinquadflatpack(TQFP)aswellasa119 ballgridarray  
(BGA) and 165 fine pitch ball grid array (fBGA).  
Description  
The IDT71V65702/5902 are 3.3V high-speed 9,437,184-bit  
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x  
18.Theyaredesignedtoeliminatedeadbuscycleswhenturningthe  
busaroundbetweenreadsandwrites,orwritesandreads.Thusthey  
TM  
havebeengiventhenameZBT ,orZeroBusTurnaround.  
AddressandcontrolsignalsareappliedtotheSRAMduringone  
clock cycle, and on the next clock cycle the associated data cycle  
PinDescriptionSummary  
0
18  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/ O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
1
2
2
CE , CE , CE  
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
1
2
3
4
Individual Byte Write Selects  
Clock  
BW , BW , BW , BW  
CLK  
ADV/LD  
Advance Burst Address/Load New Address  
Linear/Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
LBO  
ZZ  
Asynchronous  
Synchronous  
Static  
I/ O0-I/O31, I/OP1-I/OP4  
Data Input/Output  
Co re Powe r, I/O Powe r  
Ground  
DD DDQ  
V
, V  
Supply  
Supply  
SS  
V
Static  
5315 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
OCTOBER 2004  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-5315/08  

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