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IDT71V65812S200PF PDF预览

IDT71V65812S200PF

更新时间： 2024-11-08 20:38:35
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
26页 532K
描述
ZBT SRAM, 512KX18, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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IDT71V65812S200PF 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：not_compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
最长访问时间：3.2 nsJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX18
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

IDT71V65812S200PF 数据手册

 浏览型号IDT71V65812S200PF的Datasheet PDF文件第2页浏览型号IDT71V65812S200PF的Datasheet PDF文件第3页浏览型号IDT71V65812S200PF的Datasheet PDF文件第4页浏览型号IDT71V65812S200PF的Datasheet PDF文件第5页浏览型号IDT71V65812S200PF的Datasheet PDF文件第6页浏览型号IDT71V65812S200PF的Datasheet PDF文件第7页 
256K x 36, 512K x 18  
Preliminary  
IDT71V65612  
IDT71V65812  
3.3V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter  
PipelinedOutputs  
Features  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle, andtwocycleslatertheassociateddatacycleoccurs, beitread  
orwrite.TheIDT71V65612/5812containdataI/O,addressandcontrol  
signalregisters.Outputenableistheonlyasynchronoussignalandcan  
beusedtodisabletheoutputsatanygiventime.  
AClockEnable(CEN)pinallowsoperationoftheIDT71V65612/5812  
to be suspended as long as necessary. All synchronous inputs are  
ignoredwhen(CEN)ishighandtheinternaldeviceregisterswillholdtheir  
previous values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
user to deselect the device when desired. If any one of these three are  
not asserted when ADV/LD is low, no new memory operation can be  
initiated. However, any pending data transfers (reads or writes) will be  
completed.Thedatabuswilltri-statetwocyclesafterchipisdeselectedor  
awriteisinitiated.  
The IDT71V65612/5812 has an on-chip burst counter. In the burst  
mode,theIDT71V65612/5812canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW) orincrementtheinternalburstcounter  
256K x 36, 512K x 18 memory configurations  
Supports high performance system speed - 200 MHz  
(3.2 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
2.5V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
Description  
The IDT71V65612/5812 are 3.3V high-speed 9,437,184-bit (ADV/LD = HIGH).  
(9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedead  
TheIDT71V65612/5812SRAMutilizeIDT'slatesthigh-performance  
bus cycles when turning the bus around between reads and writes, or CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm  
writesandreads. Thus, theyhavebeengiventhenameZBTTM, orZero 100-pinthinplasticquadflatpack(TQFP)aswellasa119 ballgridarray  
Bus Turnaround.  
(BGA) and 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1, CE  
2, CE2  
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW1, BW2, BW3, BW4  
CLK  
ADV/LD  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Static  
LBO  
TMS  
TDI  
N/A  
N/A  
TCK  
TDO  
ZZ  
Test Clock  
N/A  
Te st Data Output  
Sleep Mode  
N/A  
Asynchronous  
Synchronous  
Static  
I/ O  
0
-I/O31, I/OP1-I/OP4  
DD, VDDQ  
SS  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
Supply  
Supply  
V
Static  
5314 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
NOVEMBER 2000  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-5314/01  
1234567...26

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与IDT71V65812S200PF相关器件

型号 品牌 获取价格 描述 数据表
IDT71V658S100BG IDT

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 		ZBT SRAM, 512KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V658S133PF IDT

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 		ZBT SRAM, 512KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V658S166BG IDT

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 		ZBT SRAM, 512KX18, 3.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V658S166PF IDT

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 		ZBT SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V658S200BG IDT

获取价格

 		ZBT SRAM, 512KX18, 3.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V658S200PF IDT

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 		ZBT SRAM, 512KX18, 3.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V65902 ETC

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 		256K x 36, 512K x 18 3.3V Synchronous ZB TM SRAMs 2.5V I/O, Burst Counter Flow-Through Out
IDT71V65902S75BQ IDT

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 		ZBT SRAM, 512KX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65902S75BQG IDT

获取价格

 		ZBT SRAM, 512KX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
IDT71V65902S80BG IDT

获取价格

 		ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

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