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IDT71V432S5PFI PDF预览

IDT71V432S5PFI

更新时间: 2024-11-08 22:22:47
品牌 Logo 应用领域
艾迪悌 - IDT 计数器静态存储器
页数 文件大小 规格书
18页 269K
描述
32K x 32 CacheRAM 3.3V Synchronous SRAM Burst Counter Single Cycle Deselect

IDT71V432S5PFI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP100,.63X.87针数:100
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.91
最长访问时间:5 ns最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:1048576 bit内存集成电路类型:CACHE SRAM
内存宽度:32湿度敏感等级:3
功能数量:1端子数量:100
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX32
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.015 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.2 mA最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

IDT71V432S5PFI 数据手册

 浏览型号IDT71V432S5PFI的Datasheet PDF文件第2页浏览型号IDT71V432S5PFI的Datasheet PDF文件第3页浏览型号IDT71V432S5PFI的Datasheet PDF文件第4页浏览型号IDT71V432S5PFI的Datasheet PDF文件第5页浏览型号IDT71V432S5PFI的Datasheet PDF文件第6页浏览型号IDT71V432S5PFI的Datasheet PDF文件第7页 
32Kx32CacheRAM™  
3.3VSynchronousSRAM  
BurstCounter  
IDT71V432  
SingleCycleDeselect  
Features  
processor interfaces. The pipelined burst architecture provides cost-  
effective 3-1-1-1 secondary cache performance for processors up to  
100 MHz.  
32K x 32 memory configuration  
Supports high-performance system speed:  
The IDT71V432 CacheRAM contains write, data, address, and  
controlregisters.InternallogicallowstheCacheRAMtogenerateaself-  
timedwritebaseduponadecisionwhichcanbeleftuntiltheextremeend  
ofthewritecycle.  
CommercialandIndustrial:  
— 5ns Clock-to-DataAccess (100MHz)  
— 6ns Clock-to-DataAccess (83MHz)  
— 7ns Clock-to-DataAccess (66MHz)  
Single-cycle deselect functionality (Compatible with  
Micron Part # MT58LC32K32D7LG-XX)  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner, as the IDT71V432canprovide fourcycles ofdata for  
asingleaddresspresentedtotheCacheRAM.Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges.The  
orderofthesethreeaddresseswillbedefinedbytheinternalburstcounter  
andthe LBO inputpin.  
Operates with a single 3.3V power supply (+10/-5%)  
Packaged in a JEDEC Standard 100-pin rectangular plastic  
thin quad flatpack (TQFP).  
TheIDT71V432CacheRAMutilizes IDT's high-performance,high-  
volume 3.3V CMOS process, and is packaged in a JEDEC Standard  
Description  
The IDT71V432 is a 3.3V high-speed 1,048,576-bit CacheRAM 14mmx20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboard  
organizedas32Kx32withfullsupportofthePentium™andPowerPC™ densityinbothdesktopandnotebookapplications.  
PinDescriptionSummary  
0
14  
A –A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
0
1
CS , CS  
Chips Selects  
Output Enable  
OE  
GW  
BWE  
1,  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
2,  
3,  
4
BW BW BW BW  
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
DC  
0
31  
I/O –I/O  
Data Input/Output  
3.3V Power  
DD  
V
Power  
Ground  
SS  
V
Ground  
DC  
3104 tbl 01  
CacheRAMisatrademarkofIntegratedDeviceTechnology.  
PentiumprocessorisatrademarkofIntelCorp.  
PowerPCisatrademarkofInternationalBusinessMachines,Inc.  
AUGUST 2001  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-3104/05  

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