ADVANCE
INFORMATION
IDT71V509
128K x 8 3.3V SYNCHRONOUS SRAM
WITH ZBT AND FLOW-THROUGH
OUTPUT
Integrated Device Technology, Inc.
duringoneclockcycle, andoneclockcyclelateritsassociated
data cycle occurs, be it read or write.
The IDT71V509 contains data, address, and control signal
registers. Output Enable is the only asynchronous signal, and
can be used to disable the output at any time.
AClockEnable(CEN)pinallowsoperationoftheIDT71V509
to be suspended as long as necessary. All synchronous
inputs are ignored when CEN is high. A Chip Select (CS) pin
allows the user to deselect the device when desired. If CS is
high, no new memory operation is initiated, but any pending
data transfers (reads and writes) will still be completed.
TheIDT71V509utilizesIDT'shigh-performance3.3VCMOS
process, and is packaged in a JEDEC Standard 400-mil 44-
lead small outline J-lead plastic package (SOJ) for high board
density.
FEATURES:
• 128K x 8 memory configuration
• High speed - 66 MHz (9 ns Clock-to-Data Access)
• Flow-Through Output
• No dead cycles between Write and Read Cycles
• Low power deselect mode
• Single 3.3V power supply (±5%)
• Packaged in 44-lead SOJ
DESCRIPTION:
The IDT71V509 is a 3.3V high-speed 1,024,576-bit syn-
chronous SRAM organized as 128K x 8. It is designed to
eliminate dead cycles when turning the bus around between
reads and writes, or writes and reads. Thus, it has been given
the name ZBT , or Zero Bus Turnaround
.
Addresses and control signals are applied to the SRAM
FUNCTIONAL BLOCK DIAGRAM
D
D
Q
Q
Address
Address
SRAM
Control
Control
(WE, CS, CEN)
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
Clock
Gate
OE
Data
3618 drw 01
The IDT logo is a registered trademark and CacheRAM, Zero Bus Turnaround and ZBTare trademarks of Integrated Device Technology, Inc.
Pentium is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
COMMERCIAL TEMPERATURE RANGE
AUGUST 1996
1996 Integrated Device Technology, Inc.
11.3
DSC-3618/1
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