Datasheet > IDT71V546S_08

IDT71V546S_08

更新时间： 2024-11-10 01:13:31

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
21页	164K
描述
3.3V Synchronous SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IDT71V546S_08 数据手册

128K x 36, 3.3V Synchronous IDT71V546S/XS

SRAM with ZBT™ Feature,

Burst Counter and Pipelined Outputs

Features

◆

128K x 36 memory configuration, pipelined outputs

Supports high performance system speed - 133 MHz

(4.2 ns Clock-to-Data Access)

clock cycle, and two cycles later its associated data cycle occurs, be it

read or write.

TheIDT71V546containsdataI/O,addressandcontrolsignalregis-

ters. Outputenableistheonlyasynchronoussignalandcanbeusedto

disabletheoutputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V546 to be

suspended as long as necessary. All synchronous inputs are ignored

whenCENishighandtheinternaldeviceregisterswillholdtheirprevious

values.

Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser

todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive

whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany

burst that was in progress is stopped. However, any pending data

transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo

cyclesafterthechipisdeselectedorawriteinitiated.

◆

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized registered outputs eliminate the

need to control OE

◆

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

Single 3.3V power supply (±5%)

◆

Packaged in a JEDEC standard 100-pin TQFP package

TheIDT71V546hasanon-chipburstcounter. Intheburstmode,the

IDT71V546canprovidefourcyclesofdataforasingleaddresspresented

totheSRAM. TheorderoftheburstsequenceisdefinedbytheLBOinput

pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.

The ADV/LD signal is used to load a new external address (ADV/LD =

LOW) or increment the internal burst counter (ADV/LD = HIGH).

TheIDT71V546SRAMutilizesIDT'shigh-performance,high-volume

3.3V CMOS process, and is packaged in a JEDEC standard 14mm x

20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.

Description

The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronous SRAM organized as 128K x 36 bits. It is designed to

eliminatedeadbuscycleswhenturningthebusaroundbetweenreads

andwrites,orwritesandreads. ThusithasbeengiventhenameZBT^TM,

or Zero Bus Turn-around.

Address and control signals are applied to the SRAM during one

PinDescriptionSummary

- A16

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Three Chip Enables

Output Enable

CE1

, CE

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

, BW

CLK

ADV/LD

Advance Burst Address / Load New Address

Linear / Interleaved Burst Order

Data Input/Output

Synchronous

Static

LBO

I/O0

- I/O31, I/OP1 - I/OP4

Synchronous

Static

3.3V Power

Supply

Ground

Static

3821 tbl 01

OCTOBER 2008

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

DSC-3821/05

12 3 4 5 6 7...21

中文翻译

下载PDF

与IDT71V546S_08相关器件

型号	品牌	获取价格	描述	数据表
IDT71V546S_17	IDT	获取价格	Synchronous SRAM with ZBT Feature Burst Counter and Pipelined Outputs
IDT71V546S100PF	IDT	获取价格	128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs
IDT71V546S100PF8	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V546S100PF9	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V546S100PFG8	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V546S100PFGI8	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
IDT71V546S100PFI	IDT	获取价格	128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs
IDT71V546S100PFI8	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V546S100PFI9	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, PLASTIC, TQFP-100
IDT71V546S117PF	IDT	获取价格	128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs

与IDT71V546S_08相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

23
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

21
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

48
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

39

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V546S_08

IDT71V546S_08 数据手册

与IDT71V546S_08相关器件

与IDT71V546S_08相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V546S_08

IDT71V546S_08 数据手册

与IDT71V546S_08相关器件

与IDT71V546S_08相关文章

您还可以找

您在本页遇到什么问题？