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IDT71V546S133PFGI

更新时间： 2024-11-19 13:08:43
品牌 Logo 应用领域
艾迪悌 - IDT 计数器存储内存集成电路静态存储器时钟
页数 文件大小 规格书
20页 179K
描述
ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100

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IDT71V546S133PFGI 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFP
包装说明：LQFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.2
Is Samacsys：N最长访问时间：4.2 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：133 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.045 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.31 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

IDT71V546S133PFGI 数据手册

 浏览型号IDT71V546S133PFGI的Datasheet PDF文件第2页浏览型号IDT71V546S133PFGI的Datasheet PDF文件第3页浏览型号IDT71V546S133PFGI的Datasheet PDF文件第4页浏览型号IDT71V546S133PFGI的Datasheet PDF文件第5页浏览型号IDT71V546S133PFGI的Datasheet PDF文件第6页浏览型号IDT71V546S133PFGI的Datasheet PDF文件第7页 
128K x 36, 3.3V Synchronous  
SRAM with ZBT Feature,  
IDT71V546  
Burst Counter and Pipelined Outputs  
Features  
◆
128K x 36 memory configuration, pipelined outputs  
Supports high performance system speed - 133 MHz  
(4.2 ns Clock-to-Data Access)  
clockcycle,andtwocycles laterits associateddatacycleoccurs,beit  
read or write.  
TheIDT71V546containsdataI/O,addressandcontrolsignalregis-  
ters. Outputenableistheonlyasynchronoussignalandcanbeusedto  
disabletheoutputsatanygiventime.  
AClockEnable (CEN)pinallows operationofthe IDT71V546tobe  
suspended as long as necessary. All synchronous inputs are ignored  
whenCENishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive  
whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany  
burst that was in progress is stopped. However, any pending data  
transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo  
cyclesafterthechipisdeselectedorawriteinitiated.  
◆
◆
◆
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized registered outputs eliminate the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
Single 3.3V power supply (±5%)  
◆
◆
◆
◆
◆
◆
◆
Packaged in a JEDEC standard 100-pin TQFP package  
TheIDT71V546hasanon-chipburstcounter. Intheburstmode,the  
IDT71V546canprovidefourcyclesofdataforasingleaddresspresented  
totheSRAM. TheorderoftheburstsequenceisdefinedbytheLBOinput  
pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.  
The ADV/LD signal is used to load a new external address (ADV/LD =  
LOW) orincrementthe internalburstcounter(ADV/LD =HIGH).  
TheIDT71V546SRAMutilizesIDT'shigh-performance,high-volume  
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x  
20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.  
Description  
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)  
synchronous SRAM organized as 128K x 36 bits. It is designed to  
eliminatedeadbuscycleswhenturningthebusaroundbetweenreads  
andwrites,orwritesandreads. ThusithasbeengiventhenameZBT ,  
or Zero Bus Turn-around.  
TM  
Address and control signals are applied to the SRAM during one  
PinDescriptionSummary  
0
16  
A - A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Three Chip Enables  
Output Enable  
1
2
2
CE , CE , CE  
OE  
R/W  
CEN  
Read/Write Signal  
Clock Enable  
Individual Byte Write Selects  
Clock  
1
2
3
4
BW , BW , BW , BW  
CLK  
ADV/LD  
LBO  
Advance Burst Address / Load New Address  
Linear / Interleaved Burst Order  
Data Input/Output  
Synchronous  
Static  
0
31  
P1  
P4  
I/O - I/O , I/O - I/O  
Synchronous  
Static  
DD  
V
3.3V Power  
Supply  
Supply  
SS  
V
Ground  
Static  
3821 tbl 01  
DECEMBER 1999  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.  
1
DSC-3821/03  
©1999IntegratedDeviceTechnology,Inc.  
1234567...20

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与IDT71V546S133PFGI相关器件

型号 品牌 获取价格 描述 数据表
IDT71V546S133PFI IDT

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 		128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs
IDT71V546S133PFI8 IDT

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 		ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V546S133PFI9 IDT

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 		ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, PLASTIC, TQFP-100
IDT71V546XS IDT

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 		3.3V Synchronous SRAM
IDT71V546XS117PFG IDT

获取价格

 		ZBT SRAM, 128KX36, 4.5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
IDT71V546XS117PFGI IDT

获取价格

 		ZBT SRAM, 128KX36, 4.5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
IDT71V546XS133PFG IDT

获取价格

 		ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
IDT71V546XS133PFGI IDT

获取价格

 		ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
IDT71V547 IDT

获取价格

 		128K X 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Flow-Through Outputs
IDT71V547S IDT

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 		Synchronous SRAM

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