Datasheet > IDT71V546S133PF8

IDT71V546S133PF8

更新时间： 2024-11-19 21:14:23

品牌	Logo	应用领域
艾迪悌 - IDT		时钟静态存储器内存集成电路
页数	文件大小	规格书
21页	188K
描述
ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

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IDT71V546S133PF8 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	14 X 20 MM, PLASTIC, TQFP-100	针数：	100
Reach Compliance Code：	not_compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.2
最长访问时间：	4.2 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	133 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	4718592 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	128KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.04 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.3 mA
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	14 mm
Base Number Matches：	1

IDT71V546S133PF8 数据手册

128K x 36, 3.3V Synchronous IDT71V546S/XS

SRAM with ZBT™ Feature,

Burst Counter and Pipelined Outputs

Features

◆

128K x 36 memory configuration, pipelined outputs

Supports high performance system speed - 133 MHz

(4.2 ns Clock-to-Data Access)

clockcycle,andtwocycles laterits associateddatacycleoccurs,beit

read or write.

TheIDT71V546containsdataI/O,addressandcontrolsignalregis-

ters. Outputenableistheonlyasynchronoussignalandcanbeusedto

disabletheoutputsatanygiventime.

AClockEnable (CEN)pinallows operationofthe IDT71V546tobe

suspended as long as necessary. All synchronous inputs are ignored

whenCENishighandtheinternaldeviceregisterswillholdtheirprevious

values.

Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser

todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive

whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany

burst that was in progress is stopped. However, any pending data

transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo

cyclesafterthechipisdeselectedorawriteinitiated.

◆

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized registered outputs eliminate the

need to control OE

◆

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

Single 3.3V power supply (±5%)

◆

Packaged in a JEDEC standard 100-pin TQFP package

TheIDT71V546hasanon-chipburstcounter. Intheburstmode,the

IDT71V546canprovidefourcyclesofdataforasingleaddresspresented

totheSRAM. TheorderoftheburstsequenceisdefinedbytheLBOinput

pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.

The ADV/LD signalis usedtoloada newexternaladdress (ADV/LD =

LOW) orincrementtheinternalburstcounter(ADV/LD =HIGH).

TheIDT71V546SRAMutilizesIDT'shigh-performance,high-volume

3.3V CMOS process, and is packaged in a JEDEC standard 14mm x

20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.

Description

The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronous SRAM organized as 128K x 36 bits. It is designed to

eliminatedeadbuscycleswhenturningthebusaroundbetweenreads

andwrites,orwritesandreads. ThusithasbeengiventhenameZBT ,

or Zero Bus Turn-around.

Address and control signals are applied to the SRAM during one

PinDescriptionSummary

- A16

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Three Chip Enables

Output Enable

CE1

, CE

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

, BW

CLK

ADV/LD

Advance Burst Address / Load New Address

Linear / Interleaved Burst Order

Data Input/Output

Synchronous

Static

LBO

I/O0

- I/O31, I/OP1 - I/OP4

Synchronous

Static

VDD

3.3V Power

Supply

VSS

Ground

Static

3821 tbl 01

OCTOBER 2008

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

DSC-3821/05

12 3 4 5 6 7...21

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与IDT71V546S133PF8相关器件

型号	品牌	获取价格	描述	数据表
IDT71V546S133PF9	IDT	获取价格	ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V546S133PFG	IDT	获取价格	ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
IDT71V546S133PFGI	IDT	获取价格	ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
IDT71V546S133PFI	IDT	获取价格	128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs
IDT71V546S133PFI8	IDT	获取价格	ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V546S133PFI9	IDT	获取价格	ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, PLASTIC, TQFP-100
IDT71V546XS	IDT	获取价格	3.3V Synchronous SRAM
IDT71V546XS117PFG	IDT	获取价格	ZBT SRAM, 128KX36, 4.5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
IDT71V546XS117PFGI	IDT	获取价格	ZBT SRAM, 128KX36, 4.5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
IDT71V546XS133PFG	IDT	获取价格	ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100

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