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IDT71V546S_17 PDF预览

IDT71V546S_17

更新时间: 2024-11-20 01:17:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
21页 228K
描述
Synchronous SRAM with ZBT Feature Burst Counter and Pipelined Outputs

IDT71V546S_17 数据手册

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128K x 36, 3.3V Synchronous  
SRAM with ZBTFeature  
Burst Counter and Pipelined Outputs  
IDT71V546S  
Features  
128K x 36 memory configuration, pipelined outputs  
Supports high performance system speed - 133 MHz  
(4.2 ns Clock-to-Data Access)  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
Single 3.3V power supply ( 5%)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized registered outputs eliminate the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Packaged in a JEDEC standard 100-pin TQFP package  
Green parts available, see Ordering Information  
Functional Block Diagram  
128K x 36 BIT  
MEMORY ARRAY  
LBO  
Address A [0:16]  
D
Q
Q
Address  
CE1, CE2, CE2  
R/W  
D
Control  
CEN  
ADV/LD  
DI  
DO  
BWx  
D
Q
Control Logic  
Clk  
Mux  
Sel  
D
Output Register  
Q
Clock  
Gate  
OE  
3821 drw 01  
.
Data I/O [0:31], I/O P[1:4]  
AUGUST 2017  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.  
1
DSC-3821/07  
©2017 Integrated Device Technology, Inc.  

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