Datasheet > IDT71V546

IDT71V546

更新时间： 2024-11-18 22:35:03

品牌	Logo	应用领域
艾迪悌 - IDT		计数器静态存储器
页数	文件大小	规格书
20页	179K
描述
128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs

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IDT71V546 数据手册

128K x 36, 3.3V Synchronous

SRAM with ZBT Feature,

IDT71V546

Burst Counter and Pipelined Outputs

Features

◆

128K x 36 memory configuration, pipelined outputs

Supports high performance system speed - 133 MHz

(4.2 ns Clock-to-Data Access)

clockcycle,andtwocycles laterits associateddatacycleoccurs,beit

read or write.

TheIDT71V546containsdataI/O,addressandcontrolsignalregis-

ters. Outputenableistheonlyasynchronoussignalandcanbeusedto

disabletheoutputsatanygiventime.

AClockEnable (CEN)pinallows operationofthe IDT71V546tobe

suspended as long as necessary. All synchronous inputs are ignored

whenCENishighandtheinternaldeviceregisterswillholdtheirprevious

values.

Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser

todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive

whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany

burst that was in progress is stopped. However, any pending data

transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo

cyclesafterthechipisdeselectedorawriteinitiated.

◆

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized registered outputs eliminate the

need to control OE

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

Single 3.3V power supply (±5%)

◆

Packaged in a JEDEC standard 100-pin TQFP package

TheIDT71V546hasanon-chipburstcounter. Intheburstmode,the

IDT71V546canprovidefourcyclesofdataforasingleaddresspresented

totheSRAM. TheorderoftheburstsequenceisdefinedbytheLBOinput

pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.

The ADV/LD signal is used to load a new external address (ADV/LD =

LOW) orincrementthe internalburstcounter(ADV/LD =HIGH).

TheIDT71V546SRAMutilizesIDT'shigh-performance,high-volume

3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x

20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.

Description

The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronous SRAM organized as 128K x 36 bits. It is designed to

eliminatedeadbuscycleswhenturningthebusaroundbetweenreads

andwrites,orwritesandreads. ThusithasbeengiventhenameZBT ,

or Zero Bus Turn-around.

Address and control signals are applied to the SRAM during one

PinDescriptionSummary

A - A

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Three Chip Enables

Output Enable

CE , CE , CE

R/W

CEN

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

BW , BW , BW , BW

CLK

ADV/LD

LBO

Advance Burst Address / Load New Address

Linear / Interleaved Burst Order

Data Input/Output

Synchronous

Static

I/O - I/O , I/O - I/O

Synchronous

Static

3.3V Power

Supply

Ground

Static

3821 tbl 01

DECEMBER 1999

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

DSC-3821/03

12 3 4 5 6 7...20

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与IDT71V546相关器件

型号	品牌	获取价格	描述	数据表
IDT71V546S	IDT	获取价格	3.3V Synchronous SRAM
IDT71V546S_08	IDT	获取价格	3.3V Synchronous SRAM
IDT71V546S_17	IDT	获取价格	Synchronous SRAM with ZBT Feature Burst Counter and Pipelined Outputs
IDT71V546S100PF	IDT	获取价格	128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs
IDT71V546S100PF8	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V546S100PF9	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V546S100PFG8	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V546S100PFGI8	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
IDT71V546S100PFI	IDT	获取价格	128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs
IDT71V546S100PFI8	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

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