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IDT71V433S11PF9 PDF预览

IDT71V433S11PF9

更新时间: 2024-11-07 19:56:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
19页 625K
描述
Cache SRAM, 32KX32, 11ns, CMOS, PQFP100, PLASTIC, TQFP-100

IDT71V433S11PF9 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP,
针数:100Reach Compliance Code:compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.91最长访问时间:11 ns
其他特性:ALSO REQUIRES 3V I/O SUPPLYJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:1048576 bit内存集成电路类型:CACHE SRAM
内存宽度:32湿度敏感等级:3
功能数量:1端口数量:1
端子数量:100字数:32768 words
字数代码:32000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX32输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

IDT71V433S11PF9 数据手册

 浏览型号IDT71V433S11PF9的Datasheet PDF文件第2页浏览型号IDT71V433S11PF9的Datasheet PDF文件第3页浏览型号IDT71V433S11PF9的Datasheet PDF文件第4页浏览型号IDT71V433S11PF9的Datasheet PDF文件第5页浏览型号IDT71V433S11PF9的Datasheet PDF文件第6页浏览型号IDT71V433S11PF9的Datasheet PDF文件第7页 
IDT71V433  
32K x 32  
3.3V Synchronous SRAM  
Flow-Through Outputs  
Features  
32K x 32 memory configuration  
The IDT71V433 SRAM contains write, data-input, address and  
controlregisters.There are noregisters inthe data outputpath(flow-  
througharchitecture). Internallogicallows the SRAMtogenerate a  
self-timed write based upon a decision which can be left until the  
extreme end of the write cycle.  
The burstmode feature offers the highestlevelofperformance to  
thesystemdesigner,astheIDT71V433canprovidefourcyclesofdata  
forasingleaddresspresentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
access sequence.Thefirstcycleofoutputdatawillflow-throughfrom  
the arrayaftera clock-to-data access time delayfromthe risingclock  
edgeofthesamecycle. Ifburstmodeoperationisselected(ADV=LOW),  
the subsequent three cycles of output data will be available to the  
user on the next three rising clock edges. The order of these three  
addresses willbe definedbythe internalburstcounterandthe LBO  
inputpin.  
Supports high performance system speed:  
CommercialandIndustrial:  
— 11 11ns Clock-to-DataAccess (50MHz)  
— 12 12ns Clock-to-DataAccess (50MHz)  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Single 3.3V power supply (+10/-5%)  
Packaged in a JEDEC Standard 100-pin rectangular plastic  
thin quad flatpack (TQFP).  
Description  
The IDT71V433 is a 3.3V high-speed 1,048,576-bit SRAM orga-  
nized as 32K x 32 with full support of various processor interfaces  
includingthePentium™andPowerPC.Theflow-throughburstarchi-  
tectureprovidescost-effective2-1-1-1performanceforprocessorsupto  
50MHz.  
The IDT71V433 SRAM utilizes IDT's high-performance 3.3V  
CMOSprocess,andispackagedinaJEDECStandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP).  
PinDescription  
A0A14  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS  
0
, CS  
1
Chips Selects  
Output Enable  
OE  
GW  
Global Write Enable  
Byte Write Enable  
BWE  
BW BW  
Individual Byte Write Selects  
Clock Input  
1
4
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O  
0
I/O31  
DD, VDDQ  
SS, VSSQ  
Data Input/Output  
V
Core and I/O Power Supply (3.3V)  
Array Ground, I/O Ground  
Power  
Power  
V
N/A  
3729 tbl 01  
PentiumisatrademarkofIntelCorp.  
PowerPCisatrademarkofInternationalBusinessMachines,Inc.  
AUGUST 2001  
1
DSC-3729/04  
©2000IntegratedDeviceTechnology,Inc.  

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