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IDT71V432S5PF8 PDF预览

IDT71V432S5PF8

更新时间: 2024-11-09 15:34:47
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
17页 242K
描述
Cache SRAM, 32KX32, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

IDT71V432S5PF8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.91最长访问时间:5 ns
最大时钟频率 (fCLK):100 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:1048576 bit
内存集成电路类型:CACHE SRAM内存宽度:32
湿度敏感等级:3功能数量:1
端子数量:100字数:32768 words
字数代码:32000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.015 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT71V432S5PF8 数据手册

 浏览型号IDT71V432S5PF8的Datasheet PDF文件第2页浏览型号IDT71V432S5PF8的Datasheet PDF文件第3页浏览型号IDT71V432S5PF8的Datasheet PDF文件第4页浏览型号IDT71V432S5PF8的Datasheet PDF文件第5页浏览型号IDT71V432S5PF8的Datasheet PDF文件第6页浏览型号IDT71V432S5PF8的Datasheet PDF文件第7页 
32Kx32CacheRAM™  
3.3VSynchronousSRAM  
BurstCounter  
IDT71V432  
SingleCycleDeselect  
Features  
LBO input selects interleaved or linear burst mode  
32K x 32 memory configuration  
Self-timed write cycle with global write control (GW),  
byte write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Operates with a single 3.3V power supply (+10/-5%)  
Packaged in a JEDEC Standard 100-pin rectangular  
plastic thin quad flatpack (TQFP)  
Supports high-performance system speed:  
CommercialandIndustrial:  
— 5nsClock-to-DataAccess(100MHz)  
— 6ns Clock-to-Data Access (83MHz)  
Single-cycle deselect functionality (Compatible with  
Micron Part # MT58LC32K32D7LG-XX)  
Green parts available, see ordering information  
Functional Block Diagram  
LBO  
ADV  
INTERNAL  
ADDRESS  
CE  
CLK  
2
Burst  
Logic  
32K x 32  
BIT  
MEMORY  
ARRAY  
Binary  
Counter  
15  
ADSC  
A0*  
CLR  
.
A1*  
ADSP  
A0, A1  
CLK EN  
2
A2–A14  
ADDRESS  
A
0
–A14  
GW  
BWE  
32  
32  
15  
REGISTER  
15  
Byte 1  
Write Register  
Byte 1  
Write Driver  
BW  
1
8
8
Byte 2  
Write Register  
Byte 2  
Write Driver  
BW2  
Byte 3  
Write Register  
Byte 3  
Write Driver  
BW  
3
8
8
Byte 4  
Write Register  
Byte 4  
Write Driver  
BW4  
OUTPUT  
REGISTER  
CE  
Q
D
CS0  
Enable  
DATA INPUT  
REGISTER  
Register  
CLK EN  
CS1  
Powerdown  
ZZ  
D
Q
Enable  
Delay  
Register  
OUTPUT  
BUFFER  
OE  
–I/O31  
32  
I/O  
0
3104 drw 01  
OCTOBER 2014  
1
©2014 Integrated Device Technology, Inc.  
DSC-3104/08  

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