Datasheet > IDT71V3576S166PF8

IDT71V3576S166PF8

更新时间： 2024-11-12 06:14:15

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
20页	363K
描述
Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100

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中文翻译

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数据手册

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128K X 36, 256K X 18

Preliminary

IDT71V3576

IDT71V3578

3.3V Synchronous SRAMs

3.3V I/O, Pipelined Outputs

Burst Counter, Single Cycle Deselect

Features

Description

◆

128K x 36, 256K x 18 memory configurations

The IDT71V3576/78 are high-speed SRAMs organized as

128Kx36/256Kx18. TheIDT71V3576/78SRAMscontainwrite, data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

Supports high system speed:

200MHz 3.1ns clock access time

183MHz 3.3ns clock access time

166MHz 3.5ns clock access time

150MHz 3.8ns clock access time

133MHz 4.2ns clock access time

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V3576/78canprovidefourcyclesofdata

forasingleaddresspresentedtotheSRAM. Aninternalburstaddress

◆

LBO input selects interleaved or linear burst mode

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

◆

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

◆

Packaged in a JEDEC Standard 100-lead plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter

flatpack (TQFP) and 119-lead ball grid array (BGA)

and the LBOinput pin.

The IDT71V3576/78 SRAMs utilize IDTs latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-leadthinplasticquadflatpack(TQFP)aswellasa119-leadballgrid

array (BGA).

PinDescriptionSummary

A -A

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

CS , CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

(1)

¹,

²,

³,

BW BW BW BW

CLK

ADV

ADSC

ADSP

LBO

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

Asynchronous

Synchronous

N/A

I/O -I/O , I/O -I/O

Data Input / Output

Core Power, I/O Power

Ground

DD DDQ

, V

Supply

N/A

5279 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V3578.

SEPTEMBER1999

DSC-5279/3

12 3 4 5 6 7...20

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与IDT71V3576S166PF8相关器件

型号	品牌	获取价格	描述	数据表
IDT71V3576S183PF8	IDT	获取价格	Cache SRAM, 128KX36, 3.3ns, CMOS, PQFP100, PLASTIC, TQFP-100
IDT71V3576S183PF9	IDT	获取价格	Cache SRAM, 128KX36, 3.3ns, CMOS, PQFP100, PLASTIC, TQFP-100
IDT71V3576S200BG	IDT	获取价格	Cache SRAM, 128KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V3576S200BG8	IDT	获取价格	Cache SRAM, 128KX36, 3.1ns, CMOS, PBGA119, BGA-119
IDT71V3576SA	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V3576SA133BG	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V3576SA133BG8	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PBGA119, BGA-119
IDT71V3576SA133BGG	IDT	获取价格	Cache SRAM, 128KX36, 4.2ns, CMOS, PBGA119, ROHS COMPLIANT, BGA-119
IDT71V3576SA133BGG8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119
IDT71V3576SA133BGGI8	IDT	获取价格	Standard SRAM, 128KX36, 4.2ns, CMOS, PBGA119

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