5秒后页面跳转
IDT71V3576S150BQG8 PDF预览

IDT71V3576S150BQG8

更新时间: 2024-11-11 14:42:47
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
22页 622K
描述
Standard SRAM, 128KX36, 3.8ns, CMOS, PBGA165

IDT71V3576S150BQG8 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.84
最长访问时间:3.8 ns最大时钟频率 (fCLK):150 MHz
I/O 类型:COMMONJESD-30 代码:R-PBGA-B165
JESD-609代码:e1内存密度:4718592 bit
内存集成电路类型:STANDARD SRAM内存宽度:36
湿度敏感等级:3端子数量:165
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA165,11X15,40
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL电源:3.3 V
认证状态:Not Qualified最大待机电流:0.03 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.25 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOMBase Number Matches:1

IDT71V3576S150BQG8 数据手册

 浏览型号IDT71V3576S150BQG8的Datasheet PDF文件第2页浏览型号IDT71V3576S150BQG8的Datasheet PDF文件第3页浏览型号IDT71V3576S150BQG8的Datasheet PDF文件第4页浏览型号IDT71V3576S150BQG8的Datasheet PDF文件第5页浏览型号IDT71V3576S150BQG8的Datasheet PDF文件第6页浏览型号IDT71V3576S150BQG8的Datasheet PDF文件第7页 
128K x 36, 256K x 18  
IDT71V3576S  
IDT71V3578S  
IDT71V3576SA  
IDT71V3578SA  
3.3VSynchronousSRAMs  
3.3VI/O,PipelinedOutputs  
BurstCounter,SingleCycleDeselect  
Features  
Description  
128K x 36, 256K x 18 memory configurations  
The IDT71V3576/78 are high-speed SRAMs organized as  
128Kx36/256Kx18.TheIDT71V3576/78SRAMs containwrite,data,  
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate  
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof  
thewritecycle.  
Supports high system speed:  
CommercialandIndustrial:  
– 150MHz 3.8ns clock access time  
– 133MHz 4.2ns clock access time  
LBO input selects interleaved or linear burst mode  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite systemdesigner,astheIDT71V3576/78canprovidefourcyclesofdata  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
3.3V I/O  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1  
compliant)  
Packaged in a JEDEC Standard 100-pin plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball andthe LBO inputpin.  
grid array (fBGA)  
forasingleaddress presentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS  
0
, CS  
1
Chip Selects  
Output Enable  
OE  
GW  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
BWE  
BW , BW  
1
2
, BW  
3
, BW (1)  
4
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Asynchronous  
Synchronous  
N/A  
JTAG Reset (Optional)  
Sleep Mode  
TRST  
ZZ  
I/O  
0
-I/O31, I/OP1-I/OP4  
DD, VDDQ  
SS  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
Supply  
Supply  
V
N/A  
5279 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V3578.  
JANUARY 2004  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-5279/04  

与IDT71V3576S150BQG8相关器件

型号 品牌 获取价格 描述 数据表
IDT71V3576S150BQGI IDT

获取价格

Cache SRAM, 128KX36, 3.8ns, CMOS, PBGA165, ROHS COMPLIANT, FBGA-165
IDT71V3576S150BQI IDT

获取价格

128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V3576S150PF IDT

获取价格

128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V3576S150PF8 IDT

获取价格

Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V3576S150PFG IDT

获取价格

Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
IDT71V3576S150PFG8 IDT

获取价格

Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V3576S150PFGI IDT

获取价格

Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100
IDT71V3576S150PFGI8 IDT

获取价格

Standard SRAM, 128KX36, 3.8ns, CMOS, PQFP100
IDT71V3576S150PFI IDT

获取价格

128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V3576S150PFI8 IDT

获取价格

Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100