256K x 18
IDT71V3548S
IDT71V3548SA
3.3V Synchronous ZBT SRAM
3.3V I/O, Burst Counter
Pipelined Outputs
Address and control signals are applied to the SRAM during one
clockcycle,andtwocycleslatertheassociateddatacycleoccurs,beit
read or write.
The IDT71V3548 contain data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
A Clock Enable (CEN) pin allows operation of the IDT71V3548
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, anypendingdata transfers (reads orwrites)willbe
completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected
orawriteisinitiated.
The IDT71V3548 has an on-chip burst counter. In the burst
mode,theIDT71V3548canprovidefourcyclesofdataforasingleaddress
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
TheIDT71V3548SRAMsutilizeIDT's latesthigh-performanceCMOS
processandarepackagedinaJEDECstandard14mmx20mm100-pin
plasticthinquadflatpack(TQFP)as wellas a 119ballgridarray(BGA)
and 165 fine pitch ball grid array (fBGA).
Features
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256K x 18 memory configurations
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Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
cycles
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Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
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Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)
Optional Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
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Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Description
The IDT71V3548 are 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or
Zero Bus Turnaround.
PinDescriptionSummary
0
17
A -A
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
1
2
2
CE , CE , CE
Output Enable
OE
R/W
CEN
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
1
2
3
4
BW , BW , BW , BW
CLK
ADV/LD
LBO
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Te st Data Inp ut
Synchronous
Static
TMS
TDI
Synchronous
Synchronous
N/A
TCK
TDO
TRST
ZZ
Te st Clo c k
Test Data Output
Synchronous
Asynchronous
Synchronous
Synchronous
Static
JTAG Reset (Optional)
Sleep Mode
0
15
P1
P2
I/O -I/O , I/O -I/O
Data Input / Output
Core Power, I/O Power
Ground
DD DDQ
V
, V
Supply
Supply
SS
V
Static
5296 tbl 01
MAY 2002
1
©2002IntegratedDeviceTechnology,Inc.
DSC-5296/03