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IDT71V3548SA133BQI PDF预览

IDT71V3548SA133BQI

更新时间： 2024-11-26 05:22:47
品牌 Logo 应用领域
艾迪悌 - IDT 计数器存储内存集成电路静态存储器时钟
页数 文件大小 规格书
26页 487K
描述
256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs

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IDT71V3548SA133BQI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：13 X 15 MM, FBGA-165针数：165
Reach Compliance Code：not_compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.3
Is Samacsys：N最长访问时间：4.2 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：133 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：15 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：165
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：225
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.045 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.31 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn63Pb37)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：13 mmBase Number Matches：1

IDT71V3548SA133BQI 数据手册

 浏览型号IDT71V3548SA133BQI的Datasheet PDF文件第2页浏览型号IDT71V3548SA133BQI的Datasheet PDF文件第3页浏览型号IDT71V3548SA133BQI的Datasheet PDF文件第4页浏览型号IDT71V3548SA133BQI的Datasheet PDF文件第5页浏览型号IDT71V3548SA133BQI的Datasheet PDF文件第6页浏览型号IDT71V3548SA133BQI的Datasheet PDF文件第7页 
256K x 18  
IDT71V3548S  
IDT71V3548SA  
3.3V Synchronous ZBT SRAM  
3.3V I/O, Burst Counter  
Pipelined Outputs  
Address and control signals are applied to the SRAM during one  
clockcycle,andtwocycleslatertheassociateddatacycleoccurs,beit  
read or write.  
The IDT71V3548 contain data I/O, address and control signal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V3548  
to be suspended as long as necessary. All synchronous inputs are  
ignored when (CEN) is high and the internal device registers will hold  
their previous values.  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
to deselect the device when desired. If any one of these three are not  
asserted when ADV/LD is low, no new memory operation can be  
initiated. However, anypendingdata transfers (reads orwrites)willbe  
completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected  
orawriteisinitiated.  
The IDT71V3548 has an on-chip burst counter. In the burst  
mode,theIDT71V3548canprovidefourcyclesofdataforasingleaddress  
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe  
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst  
sequence. The ADV/LD signal is used to load a new external address  
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =  
HIGH).  
TheIDT71V3548SRAMsutilizeIDT's latesthigh-performanceCMOS  
processandarepackagedinaJEDECstandard14mmx20mm100-pin  
plasticthinquadflatpack(TQFP)as wellas a 119ballgridarray(BGA)  
and 165 fine pitch ball grid array (fBGA).  
Features  
◆
256K x 18 memory configurations  
◆
Supports high performance system speed - 133 MHz  
(4.2 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
◆
◆
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
◆
◆
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)  
Optional Boundary Scan JTAG Interface (IEEE 1149.1  
compliant)  
◆
◆
◆
◆
◆
◆
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
Description  
The IDT71V3548 are 3.3V high-speed 4,718,592-bit (4.5 Megabit)  
synchronous SRAMS. They are designed to eliminate dead bus  
cycles when turning the bus around between reads and writes, or  
writes and reads. Thus, they have been given the name ZBTTM, or  
Zero Bus Turnaround.  
PinDescriptionSummary  
0
17  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
1
2
2
CE , CE , CE  
Output Enable  
OE  
R/W  
CEN  
Read/Write Signal  
Clock Enable  
Individual Byte Write Selects  
Clock  
1
2
3
4
BW , BW , BW , BW  
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Te st Data Inp ut  
Synchronous  
Static  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
TRST  
ZZ  
Te st Clo c k  
Test Data Output  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Static  
JTAG Reset (Optional)  
Sleep Mode  
0
15  
P1  
P2  
I/O -I/O , I/O -I/O  
Data Input / Output  
Core Power, I/O Power  
Ground  
DD DDQ  
V
, V  
Supply  
Supply  
SS  
V
Static  
5296 tbl 01  
MAY 2002  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5296/03  
1234567...26

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