5秒后页面跳转
捷配首页

Datasheet > IDT71V3548S133PFI9
IDT71V3548S133PFI9 PDF预览

IDT71V3548S133PFI9

更新时间： 2024-11-26 14:51:27
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
26页 982K
描述
ZBT SRAM, 256KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

阅读下载

中文翻译

获取价格

IDT71V3548S133PFI9 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
Is Samacsys：N最长访问时间：4.2 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX18
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

IDT71V3548S133PFI9 数据手册

 浏览型号IDT71V3548S133PFI9的Datasheet PDF文件第2页浏览型号IDT71V3548S133PFI9的Datasheet PDF文件第3页浏览型号IDT71V3548S133PFI9的Datasheet PDF文件第4页浏览型号IDT71V3548S133PFI9的Datasheet PDF文件第5页浏览型号IDT71V3548S133PFI9的Datasheet PDF文件第6页浏览型号IDT71V3548S133PFI9的Datasheet PDF文件第7页 
256K x 18  
IDT71V3548S  
IDT71V3548SA  
3.3V Synchronous ZBT SRAM  
3.3V I/O, Burst Counter  
Pipelined Outputs  
Address and control signals are applied to the SRAM during one  
clockcycle,andtwocycleslatertheassociateddatacycleoccurs,beit  
read or write.  
The IDT71V3548 contain data I/O, address and control signal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V3548  
to be suspended as long as necessary. All synchronous inputs are  
ignored when (CEN) is high and the internal device registers will hold  
their previous values.  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
to deselect the device when desired. If any one of these three are not  
asserted when ADV/LD is low, no new memory operation can be  
initiated. However, anypendingdata transfers (reads orwrites)willbe  
completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected  
orawriteisinitiated.  
The IDT71V3548 has an on-chip burst counter. In the burst  
mode,theIDT71V3548canprovidefourcyclesofdataforasingleaddress  
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe  
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst  
sequence. The ADV/LD signal is used to load a new external address  
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =  
HIGH).  
TheIDT71V3548SRAMsutilizeIDT's latesthigh-performanceCMOS  
processandarepackagedinaJEDECstandard14mmx20mm100-pin  
plasticthinquadflatpack(TQFP)as wellas a 119ballgridarray(BGA)  
and 165 fine pitch ball grid array (fBGA).  
Features  
◆
256K x 18 memory configurations  
◆
Supports high performance system speed - 133 MHz  
(4.2 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
◆
◆
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
◆
◆
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)  
Optional Boundary Scan JTAG Interface (IEEE 1149.1  
compliant)  
◆
◆
◆
◆
◆
◆
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
Description  
The IDT71V3548 are 3.3V high-speed 4,718,592-bit (4.5 Megabit)  
synchronous SRAMS. They are designed to eliminate dead bus  
cycles when turning the bus around between reads and writes, or  
writes and reads. Thus, they have been given the name ZBTTM, or  
Zero Bus Turnaround.  
PinDescriptionSummary  
0
17  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
1
2
2
CE , CE , CE  
Output Enable  
OE  
R/W  
CEN  
Read/Write Signal  
Clock Enable  
Individual Byte Write Selects  
Clock  
1
2
3
4
BW , BW , BW , BW  
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Te st Data Inp ut  
Synchronous  
Static  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
TRST  
ZZ  
Te st Clo c k  
Test Data Output  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Static  
JTAG Reset (Optional)  
Sleep Mode  
0
15  
P1  
P2  
I/O -I/O , I/O -I/O  
Data Input / Output  
Core Power, I/O Power  
Ground  
DD DDQ  
V
, V  
Supply  
Supply  
SS  
V
Static  
5296 tbl 01  
MAY 2002  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5296/03  
1234567...26

中文翻译

下载PDF

与IDT71V3548S133PFI9相关器件

型号 品牌 获取价格 描述 数据表
IDT71V3548SA IDT

获取价格

 		256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3548SA100B IDT

获取价格

 		ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V3548SA100BG IDT

获取价格

 		256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3548SA100BG8 IDT

获取价格

 		ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V3548SA100BGI IDT

获取价格

 		256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3548SA100BQ IDT

获取价格

 		256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3548SA100BQG IDT

获取价格

 		ZBT SRAM, 256KX18, 5ns, CMOS, PBGA165, 13 X 15 MM, GREEN, FBGA-165
IDT71V3548SA100BQI IDT

获取价格

 		256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3548SA100PF IDT

获取价格

 		256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3548SA100PFI IDT

获取价格

 		256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs

与IDT71V3548S133PFI9相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证