Datasheet > IDT71V3548S133PFG8

IDT71V3548S133PFG8

更新时间： 2024-11-27 07:20:31

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
26页	982K
描述
ZBT SRAM, 256KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-100

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IDT71V3548S133PFG8 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.62
最长访问时间：	4.2 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
内存密度：	4718592 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	18	功能数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm

IDT71V3548S133PFG8 数据手册

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256K x 18

IDT71V3548S

IDT71V3548SA

3.3V Synchronous ZBT SRAM

3.3V I/O, Burst Counter

Pipelined Outputs

Address and control signals are applied to the SRAM during one

clockcycle,andtwocycleslatertheassociateddatacycleoccurs,beit

read or write.

The IDT71V3548 contain data I/O, address and control signal

registers.Outputenableistheonlyasynchronoussignalandcanbeused

todisabletheoutputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V3548

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser

to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be

initiated. However, anypendingdata transfers (reads orwrites)willbe

completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected

orawriteisinitiated.

The IDT71V3548 has an on-chip burst counter. In the burst

mode,theIDT71V3548canprovidefourcyclesofdataforasingleaddress

presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe

LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst

sequence. The ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =

HIGH).

TheIDT71V3548SRAMsutilizeIDT's latesthigh-performanceCMOS

processandarepackagedinaJEDECstandard14mmx20mm100-pin

plasticthinquadflatpack(TQFP)as wellas a 119ballgridarray(BGA)

and 165 fine pitch ball grid array (fBGA).

Features

◆

256K x 18 memory configurations

◆

Supports high performance system speed - 133 MHz

(4.2 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

cycles

◆

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

◆

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)

Optional Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

◆

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

Description

The IDT71V3548 are 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronous SRAMS. They are designed to eliminate dead bus

cycles when turning the bus around between reads and writes, or

writes and reads. Thus, they have been given the name ZBT^TM, or

Zero Bus Turnaround.

PinDescriptionSummary

A -A

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE , CE , CE

Output Enable

R/W

CEN

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

BW , BW , BW , BW

CLK

ADV/LD

LBO

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Te st Data Inp ut

Synchronous

Static

TMS

TDI

Synchronous

N/A

TCK

TDO

TRST

Te st Clo c k

Test Data Output

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

I/O -I/O , I/O -I/O

Data Input / Output

Core Power, I/O Power

Ground

DD DDQ

, V

Supply

Static

5296 tbl 01

MAY 2002

DSC-5296/03

12 3 4 5 6 7...26

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与IDT71V3548S133PFG8相关器件

型号	品牌	获取价格	描述	数据表
IDT71V3548S133PFGI	IDT	获取价格	ZBT SRAM, 256KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V3548S133PFI	IDT	获取价格	256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3548S133PFI9	IDT	获取价格	ZBT SRAM, 256KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V3548SA	IDT	获取价格	256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3548SA100B	IDT	获取价格	ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V3548SA100BG	IDT	获取价格	256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3548SA100BG8	IDT	获取价格	ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V3548SA100BGI	IDT	获取价格	256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3548SA100BQ	IDT	获取价格	256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3548SA100BQG	IDT	获取价格	ZBT SRAM, 256KX18, 5ns, CMOS, PBGA165, 13 X 15 MM, GREEN, FBGA-165

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