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IDT71V321S55TFI8 PDF预览

IDT71V321S55TFI8

更新时间: 2024-11-26 18:40:27
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
15页 133K
描述
Multi-Port SRAM, 2KX8, 55ns, CMOS, PQFP64

IDT71V321S55TFI8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:not_compliant
风险等级:5.57最长访问时间:55 ns
I/O 类型:COMMONJESD-30 代码:S-PQFP-G64
JESD-609代码:e0内存密度:16384 bit
内存集成电路类型:MULTI-PORT SRAM内存宽度:8
湿度敏感等级:3端口数量:2
端子数量:64字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified最大待机电流:0.005 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.115 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

IDT71V321S55TFI8 数据手册

 浏览型号IDT71V321S55TFI8的Datasheet PDF文件第2页浏览型号IDT71V321S55TFI8的Datasheet PDF文件第3页浏览型号IDT71V321S55TFI8的Datasheet PDF文件第4页浏览型号IDT71V321S55TFI8的Datasheet PDF文件第5页浏览型号IDT71V321S55TFI8的Datasheet PDF文件第6页浏览型号IDT71V321S55TFI8的Datasheet PDF文件第7页 
IDT71V321S/L  
IDT71V421S/L  
HIGH SPEED 3.3V  
2K X 8 DUAL-PORT  
STATIC RAM WITH INTERRUPTS  
Features  
On-chip port arbitration logic (IDT71V321 only)  
High-speed access  
BUSY output flag on IDT71V321; BUSY input on IDT71V421  
Fully asynchronous operation from either port  
Battery backup operation2V data retention (L only)  
TTL-compatible, single 3.3V power supply  
Available in 52-pin PLCC, 64-pin TQFP and STQFP  
packages  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Green parts available, see ordering information  
– Commercial: 25/35/55ns (max.)  
Industrial: 25ns (max.)  
Low-power operation  
IDT71V321/IDT71V421S  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
IDT71V321/V421L  
Active: 325mW (typ.)  
Standby: 1mW (typ.)  
Two INT flags for port-to-port communications  
MASTER IDT71V321 easily expands data bus width to 16-  
or-more-bits using SLAVE IDT71V421  
FunctionalBlockDiagram  
OE  
R
R
OE  
L
CE  
R/W  
CEL  
R
R/W  
L
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
(1,2)  
BUSYR  
BUSY  
L
A
10L  
A
A
10R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
11  
11  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CE  
OE  
R/W  
L
CE  
OE  
R/W  
R
R
L
R
L
(2)  
(2)  
L
INTR  
INT  
3026 drw 01  
NOTES:  
1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input.  
2. BUSY and INT are totem-pole outputs.  
AUGUST 2006  
1
DSC-3026/10  
©2006IntegratedDeviceTechnology,Inc.  

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