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IDT70V7339S200BC PDF预览

IDT70V7339S200BC

更新时间: 2024-10-28 22:26:15
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
22页 484K
描述
HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

IDT70V7339S200BC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:BGA
包装说明:LBGA, BGA256,16X16,40针数:256
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.32
最长访问时间:10 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):200 MHzI/O 类型:COMMON
JESD-30 代码:S-PBGA-B256JESD-609代码:e0
长度:17 mm内存密度:9437184 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端口数量:2端子数量:256
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA256,16X16,40
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:2.5/3.3,3.3 V认证状态:Not Qualified
座面最大高度:1.5 mm最大待机电流:0.03 A
最小待机电流:3.15 V子类别:SRAMs
最大压摆率:0.95 mA最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:17 mmBase Number Matches:1

IDT70V7339S200BC 数据手册

 浏览型号IDT70V7339S200BC的Datasheet PDF文件第2页浏览型号IDT70V7339S200BC的Datasheet PDF文件第3页浏览型号IDT70V7339S200BC的Datasheet PDF文件第4页浏览型号IDT70V7339S200BC的Datasheet PDF文件第5页浏览型号IDT70V7339S200BC的Datasheet PDF文件第6页浏览型号IDT70V7339S200BC的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V 512K x 18  
SYNCHRONOUS  
BANK-SWITCHABLE  
IDT70V7339S  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
Features:  
– 1.5ns setup to clock and 0.5ns hold on all control, data, and  
address inputs @ 200MHz  
512K x 18 Synchronous Bank-Switchable Dual-ported  
Data input, address, byte enable and control registers  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
LVTTL- compatible, 3.3V (±150mV) power supply  
for core  
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V  
(±100mV) power supply for I/Os and control signals on  
each port  
Industrial temperature range (-40°C to +85°C) is  
available at 166MHz and 133MHz  
Available in a 144-pin Thin Quad Flatpack (TQFP),  
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball  
GridArray(BGA)  
Supports JTAG features compliant with IEEE 1149.1  
Due to limited pin count, JTAG is not supported on the  
144-pin TQFP package.  
SRAM Architecture  
64 independent 8K x 18 banks  
– 9 megabits of memory on chip  
Bank access controlled via bank address pins  
High-speed data access  
– Commercial:3.4ns (200MHz)/3.6ns (166MHz)/  
4.2ns (133MHz) (max.)  
Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)  
Selectable Pipelined or Flow-Through output mode  
Counter enable and repeat features  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
– 5ns cycle time, 200MHzoperation(14Gbps bandwidth)  
– Fast 3.4ns clock to data out  
FunctionalBlockDiagram  
PL/  
FT  
OPTL  
CLKL  
L
PL/FTR  
OPTR  
CLKR  
ADSL  
CNTENL  
REPEATL  
R/WL  
ADSR  
CNTENR  
REPEATR  
R/WR  
CE0R  
CE1R  
UBR  
LBR  
MUX  
CONTROL  
LOGIC  
CONTROL  
LOGIC  
CE0L  
CE1L  
UBL  
LBL  
8Kx18  
MEMORY  
ARRAY  
OEL  
OER  
(BANK 0)  
MUX  
MUX  
I/O  
CONTROL  
I/O  
CONTROL  
I/O0L-17L  
I/O0R-17R  
8Kx18  
MEMORY  
ARRAY  
A12R  
A0R  
(BANK 1)  
A12L  
A0L  
ADDRESS  
DECODE  
ADDRESS  
DECODE  
MUX  
BA5R  
BA4R  
BA3R  
BA2R  
BA1R  
BA0R  
BA5L  
BA4L  
3L  
BANK  
DECODE  
BA  
BA  
BANK  
DECODE  
2L  
BA1L  
BA0L  
MUX  
8Kx18  
MEMORY  
ARRAY  
(BANK 63)  
NOTE:  
MUX  
JTAG  
1
1. The Bank-Switchable dual-port uses a true SRAM  
core instead of the traditional dual-port SRAM core.  
As a result, it has unique operating characteristics.  
Please refer to the functional description on page 19  
for details.  
,
5628 drw 01  
TMS  
TCK  
TDI  
TDO  
TRST  
DECEMBER 2002  
DSC 5628/6  
©2002IntegratedDeviceTechnology,Inc.  

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