HIGH-SPEED 3.3V 512K x 18
SYNCHRONOUS
BANK-SWITCHABLE
IDT70V7339S
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
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512K x 18 Synchronous Bank-Switchable Dual-ported
– Data input, address, byte enable and control registers
– Self-timedwriteallowsfastcycletime
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 144-pin Thin Quad Flatpack (TQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
GridArray(BGA)
Supports JTAG features compliant with IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
144-pin TQFP package.
SRAM Architecture
– 64 independent 8K x 18 banks
– 9 megabits of memory on chip
Bank access controlled via bank address pins
High-speed data access
– Commercial:3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 5ns cycle time, 200MHzoperation(14Gbps bandwidth)
– Fast 3.4ns clock to data out
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FunctionalBlockDiagram
PL/
FT
OPTL
CLKL
L
PL/FTR
OPTR
CLKR
ADSL
CNTENL
REPEATL
R/WL
ADSR
CNTENR
REPEATR
R/WR
CE0R
CE1R
UBR
LBR
MUX
CONTROL
LOGIC
CONTROL
LOGIC
CE0L
CE1L
UBL
LBL
8Kx18
MEMORY
ARRAY
OEL
OER
(BANK 0)
MUX
MUX
I/O
CONTROL
I/O
CONTROL
I/O0L-17L
I/O0R-17R
8Kx18
MEMORY
ARRAY
A12R
A0R
(BANK 1)
A12L
A0L
ADDRESS
DECODE
ADDRESS
DECODE
MUX
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
BA5L
BA4L
3L
BANK
DECODE
BA
BA
BANK
DECODE
2L
BA1L
BA0L
MUX
8Kx18
MEMORY
ARRAY
(BANK 63)
NOTE:
MUX
JTAG
1
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
,
5628 drw 01
TMS
TCK
TDI
TDO
TRST
DECEMBER 2002
DSC 5628/6
©2002IntegratedDeviceTechnology,Inc.