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IDT70V7278S PDF预览

IDT70V7278S

更新时间: 2024-10-29 12:20:31
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
16页 130K
描述
HIGH-SPEED 3.3V 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS

IDT70V7278S 数据手册

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HIGH-SPEED 3.3V  
IDT70V7278S/L  
32K x 16 BANK-SWITCHABLE  
DUAL-PORTED SRAM WITH  
EXTERNAL BANK SELECTS  
Features  
32K x 16 Bank-Switchable Dual-Ported SRAM Architecture  
– Four independent 8K x 16 banks  
Interrupt flags with programmable masking  
Dual Chip Enables allow for depth expansion without  
external logic  
UB and LB are available for x8 or x16 bus matching  
LVTTL-compatible, single 3.3V (±5%) power supply  
Available in a 100-pin Thin Quad Flatpack  
Industrial temperature range (-40° to +85°C) is available  
for selected speeds  
– 512 kilobit of memory on chip  
Fast asynchronous address-to-data access time: 15ns  
User-controlled input pins included for bank selects  
Independent port controls with asynchronous address &  
data busses  
Four 16-bit mailboxes available to each port for inter-  
processor communications; interrupt option  
Functional Block Diagram  
MUX  
R/W  
CE0L  
CE1L  
L
R/W  
CE0R  
CE1R  
R
8Kx16  
MEMORY  
ARRAY  
(BANK 0)  
CONTROL  
LOGIC  
CONTROL  
LOGIC  
UB  
LB  
OE  
L
L
L
UB  
LB  
OE  
R
R
R
MUX  
MUX  
I/O  
CONTROL  
I/O  
CONTROL  
I/O8L-15L  
I/O0L-7L  
I/O8R-15R  
I/O0R-7R  
8Kx16  
MEMORY  
ARRAY  
(BANK 1)  
A
12L  
A
12R  
ADDRESS  
DECODE  
ADDRESS  
DECODE  
(1)  
(1)  
0R  
A0L  
A
MUX  
BA1R  
BA0R  
BA1L  
BA0L  
BANK  
DECODE  
BANK  
DECODE  
MUX  
8Kx16  
MEMORY  
ARRAY  
(BANK 3)  
MUX  
(2)  
3
BKSEL  
BKSEL  
BANK  
SELECT  
(2)  
0
(1)  
(1)  
(1)  
(1)  
A
A
5R  
0R  
A
A
5L  
0L  
MAILBOX  
INTERRUPT  
LOGIC  
LBR/UBR  
LB  
L
/UB  
OE  
R/W  
CE  
L
OE  
R
L
R/WR  
L
CE  
R
L
MBSEL  
L
L
MBSEL  
R
4078 drw 01  
INT  
INTR  
NOTES:  
1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins serve as mailbox  
address inputs.  
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for more details.  
JUNE 2000  
1
DSC-4078/7  
©2000IntegratedDeviceTechnology,Inc.  

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