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IDT70V3379S6BCGI PDF预览

IDT70V3379S6BCGI

更新时间: 2024-11-09 15:34:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
17页 186K
描述
Dual-Port SRAM, 32KX18, 6ns, PBGA256, BGA-256

IDT70V3379S6BCGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:LBGA,针数:256
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.45
最长访问时间:6 nsJESD-30 代码:S-PBGA-B256
JESD-609代码:e1长度:17 mm
内存密度:589824 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:256
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX18
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.5 mm
最大供电电压 (Vsup):3.45 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:17 mm
Base Number Matches:1

IDT70V3379S6BCGI 数据手册

 浏览型号IDT70V3379S6BCGI的Datasheet PDF文件第2页浏览型号IDT70V3379S6BCGI的Datasheet PDF文件第3页浏览型号IDT70V3379S6BCGI的Datasheet PDF文件第4页浏览型号IDT70V3379S6BCGI的Datasheet PDF文件第5页浏览型号IDT70V3379S6BCGI的Datasheet PDF文件第6页浏览型号IDT70V3379S6BCGI的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V 32K x 18  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
IDT70V3379S  
Features:  
address inputs @ 133MHz  
Data input, address, byte enable and control registers  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
LVTTL- compatible, single 3.3V (±150mV) power supply for  
core  
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)  
power supply for I/Os and control signals on each port  
Industrial temperature range (-40°C to +85°C) is  
available for selected speeds  
Available in a 128-pin Thin Quad Plastic Flatpack (TQFP)  
and 208-pin fine pitch Ball Grid Array, and 256-pin  
BallGridArray  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:4.2/5/6ns (max.)  
Industrial:5/6ns (max)  
Pipelined output mode  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
– 7.5ns cycle time, 133MHzoperation(9.6Gbps bandwidth)  
– Fast 4.2ns clock to data out  
– 1.8ns setup to clock and 0.7ns hold on all control, data, and  
FunctionalBlockDiagram  
UBL  
UBR  
LBR  
L
LB  
R/WL  
R/WR  
B
B
B B  
W W  
W W  
0
L
1
L
1
R
0
R
CE0L  
CE0R  
1L  
CE  
1R  
CE  
OEL  
OER  
Dout0-8_L  
Dout9-17_L  
Dout0-8_R  
Dout9-17_R  
32K x 18  
MEMORY  
ARRAY  
,
.
I/O0 L - I/O1 7 L  
Din_L  
Din_R  
I/O0R - I/O17R  
L
CLK  
CLKR  
A14L  
A14R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A0L  
A0R  
ADDR_L  
ADDR_R  
L
CNTRST  
R
CNTRST  
ADSR  
L
ADS  
CNTENL  
CNTENR  
4833 tbl 01  
APRIL 2001  
1
DSC 4833/8  
©2001IntegratedDeviceTechnology,Inc.  

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