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IDT70V3389S

更新时间: 2024-11-08 23:01:07
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
17页 177K
描述
HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

IDT70V3389S 数据手册

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HIGH-SPEED 3.3V 64K x 18  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
IDT70V3389S  
Features  
address inputs @ 133MHz  
Data input, address, byte enable and control registers  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
LVTTL- compatible, single 3.3V (±150mV) power supply for  
core  
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)  
power supply for I/Os and control signals on each port  
Industrial temperature range (-40°C to +85°C) is  
available for selected speeds  
Available in a 128-pin Thin Quad Plastic Flatpack (TQFP),  
208-pin fine pitch Ball Grid Array, and 256-pin Ball  
GridArray  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:4.2/5/6ns (max.)  
Industrial:5/6ns (max)  
Pipelined output mode  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
– 7.5ns cycle time, 133MHzoperation(9.6Gbps bandwidth)  
– Fast 4.2ns clock to data out  
– 1.8ns setup to clock and 0.7ns hold on all control, data, and  
FunctionalBlockDiagram  
UBL  
LBL  
UBR  
LBR  
L
R/W  
WR  
R/  
B
B
B B  
W W  
W W  
0
L
1
L
1
R
0
R
0L  
CE  
0R  
CE  
1L  
CE  
1R  
CE  
OEL  
OER  
Dout0-8_L  
Dout9-17_L  
Dout0-8_R  
Dout9-17_R  
64K x 18  
MEMORY  
ARRAY  
I/O0 L - I/O1 7 L  
Din_L  
0R  
17R  
R
Din_R  
I/O - I/O  
CLKL  
CLK  
A15L  
A15R  
A0R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A0L  
CNTRSTL  
ADSL  
.
ADDR_L  
ADDR_R  
CNTRSTR  
R
ADS  
L
R
CNTEN  
CNTEN  
4832 tbl 01  
APRIL 2001  
1
DSC 4832/8  
©2001IntegratedDeviceTechnology,Inc.  

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