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IDT70V05L35G PDF预览

IDT70V05L35G

更新时间: 2024-09-16 22:57:19
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器
页数 文件大小 规格书
17页 241K
描述
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

IDT70V05L35G 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:PGA
包装说明:1.180 X 1.180 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-68针数:68
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.43
Is Samacsys:N最长访问时间:35 ns
其他特性:INTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWNI/O 类型:COMMON
JESD-30 代码:S-CPGA-P68JESD-609代码:e0
长度:29.464 mm内存密度:65536 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
功能数量:1端口数量:2
端子数量:68字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX8输出特性:3-STATE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装等效代码:PGA68,11X11封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:5.207 mm
最大待机电流:0.005 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.155 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
处于峰值回流温度下的最长时间:30宽度:29.464 mm
Base Number Matches:1

IDT70V05L35G 数据手册

 浏览型号IDT70V05L35G的Datasheet PDF文件第2页浏览型号IDT70V05L35G的Datasheet PDF文件第3页浏览型号IDT70V05L35G的Datasheet PDF文件第4页浏览型号IDT70V05L35G的Datasheet PDF文件第5页浏览型号IDT70V05L35G的Datasheet PDF文件第6页浏览型号IDT70V05L35G的Datasheet PDF文件第7页 
IDT70V05S/L  
HIGH-SPEED 3.3V  
8K x 8 DUAL-PORT  
STATIC RAM  
Integrated Device Technology, Inc.  
• On-chip port arbitration logic  
• Full on-chip hardware support of semaphore signaling  
between ports  
• Fully asynchronous operation from either port  
• Devices are capable of withstanding greater than 2001V  
electrostatic discharge  
FEATURES:  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
• High-speed access  
— Commercial: 25/35/55ns (max.)  
• Low-power operation  
• Battery backup operation—2V data retention  
— IDT70V05S  
LVTTL-compatible, single 3.3V (±0.3V) power supply  
Active: 350mW (typ.)  
Standby: 3.5mW (typ.)  
— IDT70V05L  
• Available in 68-pin PGA, 68-pin PLCC, and a 64-pin  
TQFP  
Active: 350mW (typ.)  
Standby: 1mW (typ.)  
DESCRIPTION:  
• IDT70V05 easily expands data bus width to 16 bits or  
more using the Master/Slave select when cascading  
more than one device  
• M/S = H for BUSY output flag on Master  
M/S = L for BUSY input on Slave  
• Busy and Interrupt Flags  
The IDT70V05 is a high-speed 8K x 8 Dual-Port Static  
RAM. The IDT70V05 is designed to be used as a stand-alone  
Dual-Port RAM or as a combination MASTER/SLAVE Dual-  
Port RAM for 16-bit-or-more word systems. Using the IDT  
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider  
memory system applications results in full-speed, error-free  
FUNCTIONAL BLOCK DIAGRAM  
OER  
OEL  
CEL  
CER  
R/W  
L
R/WR  
I/O0L- I/O7L  
I/O0R-I/O7R  
(1,2)  
I/O  
Control  
I/O  
Control  
BUSY (1,2)  
L
BUSY  
R
A
12L  
0L  
A
A
12R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
NOTES:  
CE  
OE  
R/W  
L
1. (MASTER):  
BUSY is output;  
(SLAVE): BUSY  
is input.  
CE  
OE  
R/W  
R
R
L
R
L
2. BUSY outputs  
and INT outputs  
are non-tri-  
SEM  
L
SEM  
R
(2)  
INT (2)  
L
INTR  
stated push-pull.  
M/S  
2941 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGE  
OCTOBER 1996  
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.  
©1996 Integrated Device Technology, Inc.  
DSC-2941/3  
6.35  
1

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