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IDT7052L25GM PDF预览

IDT7052L25GM

更新时间: 2024-10-29 05:04:27
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
11页 112K
描述
Application Specific SRAM, 2KX8, 25ns, CMOS, CPGA108

IDT7052L25GM 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:not_compliant
风险等级:5.92最长访问时间:25 ns
I/O 类型:COMMONJESD-30 代码:S-XPGA-P108
JESD-609代码:e0内存密度:16384 bit
内存集成电路类型:APPLICATION SPECIFIC SRAM内存宽度:8
端口数量:4端子数量:108
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:2KX8
输出特性:3-STATE封装主体材料:CERAMIC
封装代码:PGA封装等效代码:PGA108,12X12
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
最大待机电流:0.0018 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.3 mA
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:TIN LEAD端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
处于峰值回流温度下的最长时间:30Base Number Matches:1

IDT7052L25GM 数据手册

 浏览型号IDT7052L25GM的Datasheet PDF文件第2页浏览型号IDT7052L25GM的Datasheet PDF文件第3页浏览型号IDT7052L25GM的Datasheet PDF文件第4页浏览型号IDT7052L25GM的Datasheet PDF文件第5页浏览型号IDT7052L25GM的Datasheet PDF文件第6页浏览型号IDT7052L25GM的Datasheet PDF文件第7页 
IDT7052S/L  
HIGH-SPEED  
2K x 8 FourPortTM  
STATIC RAM  
Features  
Battery backup operation2V data retention  
TTL-compatible; single 5V (±10%) power supply  
High-speed access  
– Commercial:20/25/35ns (max.)  
Industrial:25ns (max.)  
Available in 120 pin and 132 pin Thin Quad Flatpacks and  
108 pin PGA  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Military:25/35ns(max.)  
Low-power operation  
IDT7052S  
Active:750mW(typ.)  
Standby: 7.5mW (typ.)  
IDT7052L  
Green parts available, see ordering information  
Active:750mW(typ.)  
Standby: 1.5mW (typ.)  
True FourPort memory cells which allow simultaneous  
access of the same memory locations  
Fully asynchronous operation from each of the four ports:  
Description  
TheIDT7052isahigh-speed2Kx8FourPort™StaticRAMdesigned  
to be used in systems where multiple access into a common RAM is  
required.ThisFourPortStaticRAMoffersincreasedsystemperformance  
inmultiprocessorsystemsthathaveaneedtocommunicateinrealtimeand  
alsooffersaddedbenefitforhigh-speedsystemsinwhichmultipleaccess  
is requiredinthe same cycle.  
P1, P2, P3, P4  
Versatile control for write-inhibit: separate BUSY input to  
control write-inhibit for each of the four ports  
FunctionalBlockDiagram  
R/WP1  
CEP1  
R/WP4  
CEP4  
OEP1  
OEP4  
COLUMN  
I/O  
COLUMN  
I/O0P1-I/O7P1  
BUSYP1  
I/O0P4-I/O7P4  
I/O  
BUSYP4  
PORT 1  
PORT 4  
ADDRESS  
DECODE  
LOGIC  
ADDRESS  
A0P1 - A10P1  
A0P4 - A10P4  
DECODE  
LOGIC  
MEMORY  
ARRAY  
PORT 2  
ADDRESS  
DECODE  
LOGIC  
PORT 3  
ADDRESS  
DECODE  
LOGIC  
A0P2 - A10P2  
A0P3 - A10P3  
BUSYP2  
BUSYP3  
COLUMN  
I/O  
COLUMN  
I/O  
I/O0P2-I/O7P2  
I/O0P3-I/O7P3  
OEP2  
OEP3  
CEP2  
R/WP2  
CEP3  
R/WP3  
2674 drw 01  
JULY 2006  
1
DSC 2674/12  
©2006IntegratedDeviceTechnology,Inc.  

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