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IDT7008S20J PDF预览

IDT7008S20J

更新时间: 2024-11-10 23:01:07
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
19页 167K
描述
HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM

IDT7008S20J 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:LCC
包装说明:1.15 X 1.15 INCH, 0.17 INCH HEIGHT, PLASTIC, LCC-84针数:84
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.27
最长访问时间:20 ns其他特性:INTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN; LOW POWER STANDBY MODE
I/O 类型:COMMONJESD-30 代码:S-PQCC-J84
JESD-609代码:e0长度:29.3116 mm
内存密度:524288 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8湿度敏感等级:1
功能数量:1端口数量:2
端子数量:84字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX8输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC84,1.2SQ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
座面最大高度:4.57 mm最大待机电流:0.015 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.325 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:29.3116 mmBase Number Matches:1

IDT7008S20J 数据手册

 浏览型号IDT7008S20J的Datasheet PDF文件第2页浏览型号IDT7008S20J的Datasheet PDF文件第3页浏览型号IDT7008S20J的Datasheet PDF文件第4页浏览型号IDT7008S20J的Datasheet PDF文件第5页浏览型号IDT7008S20J的Datasheet PDF文件第6页浏览型号IDT7008S20J的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7008S/L  
64K x 8 DUAL-PORT  
STATIC RAM  
Features  
IDT7008 easily expands data bus width to 16 bits or  
more using the Master/Slave select when cascading more  
than one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Interrupt Flag  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
Military:25/35/55ns(max.)  
Industrial:55ns (max.)  
– Commercial:20/25/35/55ns(max.)  
Low-power operation  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
IDT7008S  
Active:750mW(typ.)  
Standby: 5mW (typ.)  
IDT7008L  
Active:750mW(typ.)  
Standby: 1mW (typ.)  
Dual chip enables allow for depth expansion without  
external logic  
Fully asynchronous operation from either port  
TTL-compatible, single 5V (±10%) power supply  
Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
FunctionalBlockDiagram  
R/WL  
CE0L  
CE1L  
R/WR  
CE0R  
CE1R  
OEL  
OER  
I/O  
Control  
I/O  
Control  
I/O0-7L  
I/O0-7R  
(1,2)  
BUSYL  
(1,2)  
BUSYR  
64Kx8  
MEMORY  
ARRAY  
7008  
A15L  
A15R  
Address  
Decoder  
Address  
Decoder  
A0R  
A0L  
16  
16  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0L  
CE0R  
1L  
CE  
1R  
CE  
OEL  
OER  
L
R/  
W
R
R/W  
SEML  
INTL  
SEMR  
INTR  
(2)  
(2)  
M/S(1)  
3198 drw 01  
NOTES:  
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
MAY 2000  
1
DSC 3198/6  
©2000IntegratedDeviceTechnology,Inc.  

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