IDT7008S25JGB

更新时间： 2024-11-11 13:08:39

品牌	Logo	应用领域
艾迪悌 - IDT		存储内存集成电路静态存储器
页数	文件大小	规格书
19页	167K
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中文翻译

获取价格

数据手册

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IDT7008S25JGB 数据手册

HIGH-SPEED

IDT7008S/L

64K x 8 DUAL-PORT

STATIC RAM

Features

◆

IDT7008 easily expands data bus width to 16 bits or

more using the Master/Slave select when cascading more

than one device

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Interrupt Flag

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

– Military:25/35/55ns(max.)

– Industrial:55ns (max.)

– Commercial:20/25/35/55ns(max.)

Low-power operation

◆

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

– IDT7008S

Active:750mW(typ.)

Standby: 5mW (typ.)

– IDT7008L

Active:750mW(typ.)

Standby: 1mW (typ.)

Dual chip enables allow for depth expansion without

external logic

◆

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

FunctionalBlockDiagram

R/WL

CE_0L

CE1L

R/W^R

CE0R

CE_1R

OE_L

OE_R

I/O

Control

I/O

Control

I/O0-7L

I/O_0-7R

(1,2)

BUSY_L

(1,2)

BUSY_R

64Kx8

MEMORY

ARRAY

7008

A15L

A^15R

Address

Decoder

Address

Decoder

A0R

A0L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE_0L

CE_0R

OEL

OER

R/W

SEM_L

INT_L

SEM^R

INTR

(2)

M/S⁽¹⁾

3198 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S = V^IL) and an output when it is a Master (M/S = VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

MAY 2000

DSC 3198/6

12 3 4 5 6 7...19

中文翻译

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